Lines Matching defs:ccsr_rcpm_v2
261 struct ccsr_rcpm_v2 { struct
262 u8 res_00[12];
263 __be32 tph10sr0; /* Thread PH10 Status Register */
264 u8 res_10[12];
265 __be32 tph10setr0; /* Thread PH10 Set Control Register */
266 u8 res_20[12];
267 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
268 u8 res_30[12];
269 __be32 tph10psr0; /* Thread PH10 Previous Status Register */
270 u8 res_40[12];
271 __be32 twaitsr0; /* Thread Wait Status Register */
272 u8 res_50[96];
273 __be32 pcph15sr; /* Physical Core PH15 Status Register */
274 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
275 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
276 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
277 u8 res_c0[16];
278 __be32 pcph20sr; /* Physical Core PH20 Status Register */
279 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
280 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
281 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
282 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
283 u8 res_e0[12];
284 __be32 pcph30sr; /* Physical Core PH30 Status Register */
285 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
286 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
287 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
288 u8 res_100[32];
289 __be32 ippwrgatecr; /* IP Power Gating Control Register */
290 u8 res_124[12];
291 __be32 powmgtcsr; /* Power Management Control & Status Reg */
295 u8 res_134[12];
296 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
297 u8 res_150[12];
298 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
299 u8 res_160[12];
300 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
301 u8 res_170[12];
302 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
303 u8 res_180[12];
304 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
305 u8 res_190[12];
306 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
307 __be32 pctbenr; /* Physical Core Time Base Enable Reg */
308 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */
309 __be32 tbclkdivr; /* Time Base Clock Divider Register */
310 u8 res_1ac[4];
311 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
312 __be32 clpcl10sr; /* Cluster PCL10 Status Register */
313 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
314 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
315 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
316 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
317 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
318 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
319 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
320 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
321 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */
322 u8 res_1e8[8];
323 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
324 u8 res_300[3568];