Lines Matching defs:ccsr_guts
32 struct ccsr_guts { struct
33 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
34 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
35 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
38 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
39 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
40 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
41 u8 res018[0x20 - 0x18];
42 u32 porcir; /* 0x.0020 - POR Configuration Information
45 u8 res024[0x30 - 0x24];
46 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
47 u8 res034[0x40 - 0x34];
48 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
51 u8 res044[0x50 - 0x44];
52 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
55 u8 res054[0x60 - 0x54];
56 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
59 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
62 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
63 u8 res06c[0x70 - 0x6c];
64 u32 devdisr; /* 0x.0070 - Device Disable Control */
67 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
68 u8 res078[0x7c - 0x78];
69 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
72 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
75 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
78 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
81 u32 pmcdr; /* 0x.008c - 4Power management clock disable
84 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
85 u32 rstrscr; /* 0x.0094 - Reset Request Status and
88 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
89 u32 autorstsr; /* 0x.009c - Automatic reset status register */
90 u32 pvr; /* 0x.00a0 - Processor Version Register */
91 u32 svr; /* 0x.00a4 - System Version Register */
92 u8 res0a8[0xb0 - 0xa8];
93 u32 rstcr; /* 0x.00b0 - Reset Control Register */
94 u8 res0b4[0xc0 - 0xb4];
95 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
97 u8 res0c4[0x100 - 0xc4];
98 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
100 u8 res140[0x224 - 0x140];
101 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
102 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
103 u8 res22c[0x604 - 0x22c];
104 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
105 u8 res608[0x800 - 0x608];
106 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
107 u8 res804[0x900 - 0x804];
108 u32 ircr; /* 0x.0900 - Infrared Control Register */
109 u8 res904[0x908 - 0x904];
110 u32 dmacr; /* 0x.0908 - DMA Control Register */
111 u8 res90c[0x914 - 0x90c];
112 u32 elbccr; /* 0x.0914 - eLBC Control Register */
113 u8 res918[0xb20 - 0x918];
114 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
115 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
116 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
117 u8 resb2c[0xe00 - 0xb2c];
118 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
119 u8 rese04[0xe10 - 0xe04];
120 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
121 u8 rese14[0xe20 - 0xe14];
122 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
123 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
126 u8 rese28[0xf04 - 0xe28];
127 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
128 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
129 u8 resf0c[0xf2c - 0xf0c];
130 u32 itcr; /* 0x.0f2c - Internal transaction control
133 u8 resf30[0xf40 - 0xf30];
134 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
135 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */