Lines Matching refs:DRA7_CLKCTRL_INDEX
17 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) macro
20 #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
39 #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
40 #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
43 #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
44 #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
45 #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
46 #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
47 #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
48 #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
49 #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
52 #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
55 #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
63 #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
64 #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
65 #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
66 #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
67 #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
68 #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
69 #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
70 #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
71 #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
72 #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
73 #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
74 #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
75 #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
76 #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
77 #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
80 #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
81 #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
84 #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
85 #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
88 #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
89 #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
90 #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
91 #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
92 #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
93 #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
94 #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
95 #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
96 #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
97 #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
98 #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
99 #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
163 #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
164 #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
165 #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
166 #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
167 #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
168 #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
169 #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
170 #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
171 #define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)