968 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
969 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1016 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_link_rate()
1018 	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);  in drm_dp_max_link_rate()
1022 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_max_lane_count()
1024 	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;  in drm_dp_max_lane_count()
1028 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_enhanced_frame_cap()
1030 	return dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_enhanced_frame_cap()
1031 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);  in drm_dp_enhanced_frame_cap()
1035 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps3_supported()
1037 	return dpcd[DP_DPCD_REV] >= 0x12 &&  in drm_dp_tps3_supported()
1038 		dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;  in drm_dp_tps3_supported()
1042 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_tps4_supported()
1044 	return dpcd[DP_DPCD_REV] >= 0x14 &&  in drm_dp_tps4_supported()
1045 		dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;  in drm_dp_tps4_supported()
1049 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_training_pattern_mask()
1051 	return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :  in drm_dp_training_pattern_mask()
1056 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_is_branch()
1058 	return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;  in drm_dp_is_branch()
1218 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1220 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1223 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],