131 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);  in tsi148_MB_irqhandler()
152 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),  in tsi148_PERR_irqhandler()
153 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),  in tsi148_PERR_irqhandler()
154 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));  in tsi148_PERR_irqhandler()
158 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),  in tsi148_PERR_irqhandler()
159 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));  in tsi148_PERR_irqhandler()
179 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);  in tsi148_VERR_irqhandler()
180 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);  in tsi148_VERR_irqhandler()
181 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
259 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irqhandler()
260 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);  in tsi148_irqhandler()
392 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_iack_received()
414 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
418 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
427 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
431 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
452 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
543 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
636 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
639 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
641 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
643 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
645 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
647 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
649 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
907 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1069 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1072 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1074 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1076 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1078 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1080 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1082 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1388 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1390 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1404 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1409 	result = ioread32be(image->kern_base + offset);  in tsi148_master_rmw()
1412 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1796 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_busy()
1857 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1881 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
2007 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_get()
2008 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_get()
2009 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_get()
2062 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2082 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2086 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2114 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2118 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2132 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2153 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);  in tsi148_slot_get()
2220 	cbar = ioread32be(bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2232 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2267 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2483 	data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);  in tsi148_probe()
2511 	data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);  in tsi148_probe()
2614 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)  in tsi148_remove()