Lines Matching refs:iowrite32
193 iowrite32(serviced, bridge->base + LINT_STAT); in ca91cx42_irqhandler()
210 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_init()
213 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_init()
215 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_init()
226 iowrite32(0, bridge->base + LINT_MAP0); in ca91cx42_irq_init()
227 iowrite32(0, bridge->base + LINT_MAP1); in ca91cx42_irq_init()
228 iowrite32(0, bridge->base + LINT_MAP2); in ca91cx42_irq_init()
235 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_init()
246 iowrite32(0, bridge->base + VINT_EN); in ca91cx42_irq_exit()
249 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_irq_exit()
251 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); in ca91cx42_irq_exit()
291 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_irq_set()
317 iowrite32(statid << 24, bridge->base + STATID); in ca91cx42_irq_generate()
321 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
330 iowrite32(tmp, bridge->base + VINT_EN); in ca91cx42_irq_generate()
410 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
413 iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); in ca91cx42_slave_set()
414 iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); in ca91cx42_slave_set()
415 iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); in ca91cx42_slave_set()
433 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
438 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); in ca91cx42_slave_set()
656 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
727 iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); in ca91cx42_master_set()
728 iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); in ca91cx42_master_set()
729 iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); in ca91cx42_master_set()
732 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
737 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); in ca91cx42_master_set()
947 iowrite32(*(u32 *)(buf + done), addr + done); in ca91cx42_master_write()
997 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1000 iowrite32(mask, bridge->base + SCYC_EN); in ca91cx42_master_rmw()
1001 iowrite32(compare, bridge->base + SCYC_CMP); in ca91cx42_master_rmw()
1002 iowrite32(swap, bridge->base + SCYC_SWP); in ca91cx42_master_rmw()
1003 iowrite32(pci_addr, bridge->base + SCYC_ADDR); in ca91cx42_master_rmw()
1006 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1012 iowrite32(0, bridge->base + SCYC_CTL); in ca91cx42_master_rmw()
1219 iowrite32(0, bridge->base + DTBC); in ca91cx42_dma_list_exec()
1220 iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); in ca91cx42_dma_list_exec()
1232 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1236 iowrite32(val, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1243 iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS); in ca91cx42_dma_list_exec()
1354 iowrite32(lm_base, bridge->base + LM_BS); in ca91cx42_lm_set()
1355 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_set()
1442 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_attach()
1447 iowrite32(lm_ctl, bridge->base + LM_CTL); in ca91cx42_lm_attach()
1470 iowrite32(tmp, bridge->base + LINT_EN); in ca91cx42_lm_detach()
1472 iowrite32(CA91CX42_LINT_LM[monitor], in ca91cx42_lm_detach()
1484 iowrite32(tmp, bridge->base + LM_CTL); in ca91cx42_lm_detach()
1552 iowrite32(geoid << 27, bridge->base + VCSR_BS); in ca91cx42_crcsr_init()
1571 iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); in ca91cx42_crcsr_init()
1575 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_init()
1591 iowrite32(tmp, bridge->base + VCSR_CTL); in ca91cx42_crcsr_exit()
1594 iowrite32(0, bridge->base + VCSR_TO); in ca91cx42_crcsr_exit()
1861 iowrite32(0, bridge->base + LINT_EN); in ca91cx42_remove()
1864 iowrite32(0x00800000, bridge->base + LSI0_CTL); in ca91cx42_remove()
1865 iowrite32(0x00800000, bridge->base + LSI1_CTL); in ca91cx42_remove()
1866 iowrite32(0x00800000, bridge->base + LSI2_CTL); in ca91cx42_remove()
1867 iowrite32(0x00800000, bridge->base + LSI3_CTL); in ca91cx42_remove()
1868 iowrite32(0x00800000, bridge->base + LSI4_CTL); in ca91cx42_remove()
1869 iowrite32(0x00800000, bridge->base + LSI5_CTL); in ca91cx42_remove()
1870 iowrite32(0x00800000, bridge->base + LSI6_CTL); in ca91cx42_remove()
1871 iowrite32(0x00800000, bridge->base + LSI7_CTL); in ca91cx42_remove()
1872 iowrite32(0x00F00000, bridge->base + VSI0_CTL); in ca91cx42_remove()
1873 iowrite32(0x00F00000, bridge->base + VSI1_CTL); in ca91cx42_remove()
1874 iowrite32(0x00F00000, bridge->base + VSI2_CTL); in ca91cx42_remove()
1875 iowrite32(0x00F00000, bridge->base + VSI3_CTL); in ca91cx42_remove()
1876 iowrite32(0x00F00000, bridge->base + VSI4_CTL); in ca91cx42_remove()
1877 iowrite32(0x00F00000, bridge->base + VSI5_CTL); in ca91cx42_remove()
1878 iowrite32(0x00F00000, bridge->base + VSI6_CTL); in ca91cx42_remove()
1879 iowrite32(0x00F00000, bridge->base + VSI7_CTL); in ca91cx42_remove()