104 	val = ioread32(bridge->base + DGCS);  in ca91cx42_VERR_irqhandler()
121 	val = ioread32(bridge->base + DGCS);  in ca91cx42_LERR_irqhandler()
142 			vec = ioread32(bridge->base +  in ca91cx42_VIRQ_irqhandler()
164 	enable = ioread32(bridge->base + LINT_EN);  in ca91cx42_irqhandler()
165 	stat = ioread32(bridge->base + LINT_STAT);  in ca91cx42_irqhandler()
262 	tmp = ioread32(bridge->base + LINT_STAT);  in ca91cx42_iack_received()
284 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_irq_set()
314 	tmp = ioread32(bridge->base + VINT_EN);  in ca91cx42_irq_generate()
328 	tmp = ioread32(bridge->base + VINT_EN);  in ca91cx42_irq_generate()
408 	temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_set()
461 	ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);  in ca91cx42_slave_get()
463 	*vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);  in ca91cx42_slave_get()
464 	vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);  in ca91cx42_slave_get()
465 	pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);  in ca91cx42_slave_get()
654 	temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in ca91cx42_master_set()
762 	ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);  in __ca91cx42_master_get()
764 	pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);  in __ca91cx42_master_get()
765 	vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);  in __ca91cx42_master_get()
766 	pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);  in __ca91cx42_master_get()
893 		*(u32 *)(buf + done) = ioread32(addr + done);  in ca91cx42_master_read()
1009 	result = ioread32(image->kern_base + offset);  in ca91cx42_master_rmw()
1173 	tmp = ioread32(bridge->base + DGCS);  in ca91cx42_dma_busy()
1223 	val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1242 		val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1255 	val = ioread32(bridge->base + DGCS);  in ca91cx42_dma_list_exec()
1261 		val = ioread32(bridge->base + DCTL);  in ca91cx42_dma_list_exec()
1375 	*lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);  in ca91cx42_lm_get()
1376 	lm_ctl = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_get()
1421 	lm_ctl = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_attach()
1440 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_lm_attach()
1468 	tmp = ioread32(bridge->base + LINT_EN);  in ca91cx42_lm_detach()
1482 		tmp = ioread32(bridge->base + LM_CTL);  in ca91cx42_lm_detach()
1500 		slot = ioread32(bridge->base + VCSR_BS);  in ca91cx42_slot_get()
1573 	tmp = ioread32(bridge->base + VCSR_CTL);  in ca91cx42_crcsr_init()
1589 	tmp = ioread32(bridge->base + VCSR_CTL);  in ca91cx42_crcsr_exit()
1654 	data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;  in ca91cx42_probe()
1776 	data = ioread32(ca91cx42_device->base + MISC_CTL);  in ca91cx42_probe()