Lines Matching refs:via_write_reg_mask
708 via_write_reg_mask(VIACR, index, value, mask); in set_source_common()
727 via_write_reg_mask(VIASR, 0x16, value, 0x40); in set_crt_source()
799 via_write_reg_mask(VIACR, 0x36, value, 0x30); in set_crt_state()
817 via_write_reg_mask(VIASR, 0x1E, value, 0xC0); in set_dvp0_state()
835 via_write_reg_mask(VIASR, 0x1E, value, 0x30); in set_dvp1_state()
853 via_write_reg_mask(VIASR, 0x2A, value, 0x03); in set_lvds1_state()
871 via_write_reg_mask(VIASR, 0x2A, value, 0x0C); in set_lvds2_state()
904 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); in via_set_sync_polarity()
906 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); in via_set_sync_polarity()
908 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); in via_set_sync_polarity()
1022 via_write_reg_mask(RegTable[i].port, RegTable[i].index, in viafb_write_regx()
1800 via_write_reg_mask(VIACR, 0x45, 0x00, 0x01); in hw_init()
1803 via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */ in hw_init()