44 #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0)  macro
274 	write_reg_dly(gsctrl, GSCTRL);  in mbxfb_set_par()
279 	write_reg_dly(gsadr, GSADR);  in mbxfb_set_par()
284 	write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |  in mbxfb_set_par()
297 	write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);  in mbxfb_set_par()
298 	write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);  in mbxfb_set_par()
299 	write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);  in mbxfb_set_par()
300 	write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);  in mbxfb_set_par()
302 	write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);  in mbxfb_set_par()
303 	write_reg_dly((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);  in mbxfb_set_par()
304 	write_reg_dly((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);  in mbxfb_set_par()
305 	write_reg_dly((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);  in mbxfb_set_par()
306 	write_reg_dly((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);  in mbxfb_set_par()
308 	write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);  in mbxfb_set_par()
310 	write_reg_dly(DINTRE_VEVENT0_EN, DINTRE);  in mbxfb_set_par()
322 		write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);  in mbxfb_blank()
323 		write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);  in mbxfb_blank()
324 		write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);  in mbxfb_blank()
327 		write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);  in mbxfb_blank()
328 		write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK);  in mbxfb_blank()
505 	write_reg_dly(vscadr, VSCADR);  in mbxfb_ioctl_planeorder()
506 	write_reg_dly(gscadr, GSCADR);  in mbxfb_ioctl_planeorder()
591 	write_reg_dly(vbbase, VBBASE);  in mbxfb_ioctl_alphactl()
592 	write_reg_dly(gbbase, GBBASE);  in mbxfb_ioctl_alphactl()
593 	write_reg_dly(vcmsk, VCMSK);  in mbxfb_ioctl_alphactl()
594 	write_reg_dly(gdrctrl, GDRCTRL);  in mbxfb_ioctl_alphactl()
595 	write_reg_dly(gscadr, GSCADR);  in mbxfb_ioctl_alphactl()
596 	write_reg_dly(vscadr, VSCADR);  in mbxfb_ioctl_alphactl()
697 	write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |  in setup_memc()
701 	write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);  in setup_memc()
704 	write_reg_dly((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |  in setup_memc()
708 	write_reg_dly(0xc2b, LMREFRESH);  in setup_memc()
710 	write_reg_dly((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |  in setup_memc()
714 	write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);  in setup_memc()
724 	write_reg_dly(SYSCLKSRC_PLL_2, SYSCLKSRC);  in enable_clocks()
725 	write_reg_dly(PIXCLKSRC_PLL_1, PIXCLKSRC);  in enable_clocks()
726 	write_reg_dly(0x00000000, CLKSLEEP);  in enable_clocks()
733 	write_reg_dly((Core_Pll_M(0xb) | Core_Pll_N(0x1) | Core_Pll_P(0x1) |  in enable_clocks()
737 	write_reg_dly((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |  in enable_clocks()
741 	write_reg_dly(0x00000000, VOVRCLK);  in enable_clocks()
742 	write_reg_dly(PIXCLK_EN, PIXCLK);  in enable_clocks()
743 	write_reg_dly(MEMCLK_EN, MEMCLK);  in enable_clocks()
744 	write_reg_dly(0x00000001, M24CLK);  in enable_clocks()
745 	write_reg_dly(0x00000001, MBXCLK);  in enable_clocks()
746 	write_reg_dly(SDCLK_EN, SDCLK);  in enable_clocks()
747 	write_reg_dly(0x00000001, PIXCLKDIV);  in enable_clocks()
772 	write_reg_dly(gsctrl, GSCTRL);  in setup_graphics()
773 	write_reg_dly(0x00000000, GBBASE);  in setup_graphics()
774 	write_reg_dly(0x00ffffff, GDRCTRL);  in setup_graphics()
775 	write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);  in setup_graphics()
776 	write_reg_dly(0x00000000, GPLUT);  in setup_graphics()
781 	write_reg_dly(vscadr, VSCADR);  in setup_graphics()
793 	write_reg_dly(dsctrl, DSCTRL);  in setup_display()
794 	write_reg_dly(0xd0303010, DMCTRL);  in setup_display()
795 	write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);  in setup_display()
802 	write_reg_dly(SYSRST_RST, SYSRST);  in enable_controller()
805 	write_reg_dly(0xffffff0c, SYSCFG);  in enable_controller()
851 	write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);  in mbxfb_suspend()
856 	write_reg_dly(SYSRST_RST, SYSRST);  in mbxfb_suspend()
868 	write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);  in mbxfb_resume()
1015 	write_reg_dly(SYSRST_RST, SYSRST);  in mbxfb_remove()