Lines Matching refs:FP_DIVISOR_MASK
727 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
728 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
729 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
738 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
739 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
740 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
755 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
756 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
757 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
766 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
767 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
768 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
1126 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) in intelfbhw_mode_to_hw()
1128 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) in intelfbhw_mode_to_hw()
1130 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) in intelfbhw_mode_to_hw()