Lines Matching refs:pllSPLL_CNTL
662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
1469 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1470 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1484 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1485 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1496 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1497 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1498 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1503 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1504 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1505 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1659 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1864 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
2096 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()