140 			OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
149                 OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
162                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
172                 OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_disable_dynamic_mode()
183                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
188                 OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
196                 OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
202                 OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
218                 OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
258     	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
266 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_disable_dynamic_mode()
272 	OUTPLL(pllCLK_PIN_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
282 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
292 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
300 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_disable_dynamic_mode()
309 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
321  	OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
327 	OUTPLL( pllVCLK_ECP_CNTL, tmp);  in radeon_pm_disable_dynamic_mode()
346                 OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
359 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_enable_dynamic_mode()
371 		OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
378 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
383 		OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
399 		OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
404 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_enable_dynamic_mode()
431 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
440 		OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
447 		OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_pm_enable_dynamic_mode()
458 	OUTPLL( pllCLK_PWRMGT_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
463 	OUTPLL(pllCLK_PIN_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
480 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
495 		OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
506 		OUTPLL(pllPLL_PWRMGT_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
518 	OUTPLL(pllPIXCLKS_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
524 	OUTPLL(pllVCLK_ECP_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
534 		OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_enable_dynamic_mode()
542 		OUTPLL(pllMCLK_MISC, tmp);  in radeon_pm_enable_dynamic_mode()
690 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */  in radeon_pm_restore_regs()
692 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);  in radeon_pm_restore_regs()
693 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);  in radeon_pm_restore_regs()
694 	OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);  in radeon_pm_restore_regs()
695 	OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);  in radeon_pm_restore_regs()
696 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_pm_restore_regs()
697 	OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);  in radeon_pm_restore_regs()
698 	OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);  in radeon_pm_restore_regs()
699 	OUTPLL(MCLK_MISC, rinfo->save_regs[7]);  in radeon_pm_restore_regs()
701 		OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);  in radeon_pm_restore_regs()
720 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);  in radeon_pm_restore_regs()
752 		OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
756 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);  in radeon_pm_program_v2clk()
757 		OUTPLL(pllP2PLL_CNTL, 0x0000bf00);  in radeon_pm_program_v2clk()
759 		OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);  in radeon_pm_program_v2clk()
761 		OUTPLL(pllP2PLL_CNTL, 0x0000a700);  in radeon_pm_program_v2clk()
764 	OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);  in radeon_pm_program_v2clk()
766 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);  in radeon_pm_program_v2clk()
769 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);  in radeon_pm_program_v2clk()
772   	OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
796 	OUTPLL(PLL_PWRMGT_CNTL, reg);  in radeon_pm_low_current()
872 	OUTPLL( pllSCLK_CNTL, sclk_cntl);  in radeon_pm_setup_for_suspend()
879 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);		  in radeon_pm_setup_for_suspend()
889     	OUTPLL( pllMCLK_CNTL, mclk_cntl);  in radeon_pm_setup_for_suspend()
896 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);  in radeon_pm_setup_for_suspend()
908  	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);  in radeon_pm_setup_for_suspend()
923 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
945 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
953 	OUTPLL( pllMCLK_MISC, tmp);  in radeon_pm_setup_for_suspend()
980 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
990 	OUTPLL( pllPLL_PWRMGT_CNTL, tmp);  in radeon_pm_setup_for_suspend()
1045 	OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
1046 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
1047 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
1162 	OUTPLL(pllMDLL_CKO,   	cko);  in radeon_pm_enable_dll()
1163 	OUTPLL(pllMDLL_RDCKA,  	cka);  in radeon_pm_enable_dll()
1164 	OUTPLL(pllMDLL_RDCKB,	ckb);  in radeon_pm_enable_dll()
1169 	OUTPLL(pllMDLL_CKO, cko);  in radeon_pm_enable_dll()
1172 	OUTPLL(pllMDLL_CKO, cko);  in radeon_pm_enable_dll()
1176 	OUTPLL(pllMDLL_RDCKA, cka);  in radeon_pm_enable_dll()
1179 	OUTPLL(pllMDLL_RDCKA, cka);  in radeon_pm_enable_dll()
1183 	OUTPLL(pllMDLL_RDCKB, ckb);  in radeon_pm_enable_dll()
1186 	OUTPLL(pllMDLL_RDCKB, ckb);  in radeon_pm_enable_dll()
1236 	OUTPLL(pllMDLL_RDCKA, dll_value);  in radeon_pm_enable_dll_m10()
1240 	OUTPLL(pllMDLL_RDCKA, dll_value);  in radeon_pm_enable_dll_m10()
1466 	OUTPLL(pllPPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1468 	OUTPLL(pllP2PLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1470 	OUTPLL(pllSPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1472 	OUTPLL(pllMPLL_CNTL, tmp | 0x3);  in radeon_pm_all_ppls_off()
1481 	OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);  in radeon_pm_start_mclk_sclk()
1493 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);  in radeon_pm_start_mclk_sclk()
1497 	OUTPLL(pllSPLL_CNTL, tmp & ~1);  in radeon_pm_start_mclk_sclk()
1504 	OUTPLL(pllSPLL_CNTL, tmp & ~0x2);  in radeon_pm_start_mclk_sclk()
1513 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_pm_start_mclk_sclk()
1529 	OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);  in radeon_pm_start_mclk_sclk()
1532 	OUTPLL(pllMPLL_CNTL, tmp & ~0x2);  in radeon_pm_start_mclk_sclk()
1539 	OUTPLL(pllMPLL_CNTL, tmp & ~0x1);  in radeon_pm_start_mclk_sclk()
1547 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_pm_start_mclk_sclk()
1568 	OUTPLL(pllSSPLL_CNTL, 0xbf03);  in radeon_pm_m10_disable_spread_spectrum()
1571 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);  in radeon_pm_m10_disable_spread_spectrum()
1595 	OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1598 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1599 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1601 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1604 	OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1607        	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1623 	OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1624 	OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1634 	OUTPLL(pllSS_TST_CNTL, tmp);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1647 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);  in radeon_pm_restore_pixel_pll()
1652 	OUTPLL(pllPPLL_REF_DIV, tmp);  in radeon_pm_restore_pixel_pll()
1667 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);  in radeon_pm_restore_pixel_pll()
1670 	OUTPLL(pllPPLL_CNTL, tmp & ~0x2);  in radeon_pm_restore_pixel_pll()
1674 	OUTPLL(pllPPLL_CNTL, tmp & ~0x1);  in radeon_pm_restore_pixel_pll()
1678 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);  in radeon_pm_restore_pixel_pll()
1682 	OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);  in radeon_pm_restore_pixel_pll()
1780 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);  in radeon_reinitialize_M10()
1804 	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_reinitialize_M10()
1813 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_reinitialize_M10()
1845 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_reinitialize_M10()
1847 	OUTPLL(pllVCLK_ECP_CNTL, 0);  in radeon_reinitialize_M10()
1848 	OUTPLL(pllPIXCLKS_CNTL, 0);  in radeon_reinitialize_M10()
1849 	OUTPLL(pllMCLK_MISC,  in radeon_reinitialize_M10()
1856 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);  in radeon_reinitialize_M10()
1857 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);  in radeon_reinitialize_M10()
1858 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);  in radeon_reinitialize_M10()
1861 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);  in radeon_reinitialize_M10()
1862 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);  in radeon_reinitialize_M10()
1863 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);  in radeon_reinitialize_M10()
1864 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);  in radeon_reinitialize_M10()
1870 	OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);  in radeon_reinitialize_M10()
1876 	OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);  in radeon_reinitialize_M10()
1879 	OUTPLL(pllHTOTAL_CNTL, 0);  in radeon_reinitialize_M10()
1880 	OUTPLL(pllHTOTAL2_CNTL, 0);  in radeon_reinitialize_M10()
1884 	OUTPLL(pllSCLK_CNTL2, tmp);  in radeon_reinitialize_M10()
1890 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M10()
2022 	OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);  in radeon_reinitialize_M9P()
2035 	OUTPLL(pllCLK_PWRMGT_CNTL, tmp);  in radeon_reinitialize_M9P()
2044        	OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_reinitialize_M9P()
2054 	OUTPLL(pllMCLK_CNTL, tmp);  in radeon_reinitialize_M9P()
2072 	OUTPLL(pllSCLK_CNTL, tmp);  in radeon_reinitialize_M9P()
2075 	OUTPLL(pllVCLK_ECP_CNTL, 0);  in radeon_reinitialize_M9P()
2076 	OUTPLL(pllPIXCLKS_CNTL, 0);  in radeon_reinitialize_M9P()
2079 	OUTPLL(pllMCLK_MISC,  in radeon_reinitialize_M9P()
2086 	OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);  in radeon_reinitialize_M9P()
2087 	OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);  in radeon_reinitialize_M9P()
2088 	OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);  in radeon_reinitialize_M9P()
2091 	OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);  in radeon_reinitialize_M9P()
2092 	OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);  in radeon_reinitialize_M9P()
2095 	OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);  in radeon_reinitialize_M9P()
2096 	OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);  in radeon_reinitialize_M9P()
2099 	OUTPLL(pllMDLL_CKO, 0x9c009c);  in radeon_reinitialize_M9P()
2100 	OUTPLL(pllMDLL_RDCKA, 0x08830883);  in radeon_reinitialize_M9P()
2101 	OUTPLL(pllMDLL_RDCKB, 0x08830883);  in radeon_reinitialize_M9P()
2108 	OUTPLL(PLL_PWRMGT_CNTL,  tmp);  in radeon_reinitialize_M9P()
2111 	OUTPLL(pllHTOTAL_CNTL, 0);  in radeon_reinitialize_M9P()
2112 	OUTPLL(pllHTOTAL2_CNTL, 0);  in radeon_reinitialize_M9P()
2161 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M9P()
2166 	OUTPLL(pllSCLK_MORE_CNTL, tmp);  in radeon_reinitialize_M9P()
2179 	OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);  in radeon_reinitialize_M9P()
2180 	OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);  in radeon_reinitialize_M9P()
2183 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2186 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2189 	OUTPLL(pllSSPLL_CNTL, tmp);  in radeon_reinitialize_M9P()
2192 	OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/  in radeon_reinitialize_M9P()
2196 	OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);  in radeon_reinitialize_M9P()
2197 	OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);  in radeon_reinitialize_M9P()
2257 	OUTPLL(pllVCLK_ECP_CNTL, tmp);
2259 	OUTPLL(pllPIXCLKS_CNTL, tmp);
2261 	OUTPLL(MCLK_CNTL, 0xaa3f0000);
2262 	OUTPLL(SCLK_CNTL, 0xffff0000);
2263 	OUTPLL(pllMPLL_AUX_CNTL, 6);
2264 	OUTPLL(pllSPLL_AUX_CNTL, 1);
2265 	OUTPLL(MDLL_CKO, 0x9f009f);
2266 	OUTPLL(MDLL_RDCKA, 0x830083);
2267 	OUTPLL(pllMDLL_RDCKB, 0x830083);
2268 	OUTPLL(PPLL_CNTL, 0xa433);
2269 	OUTPLL(P2PLL_CNTL, 0xa433);
2270 	OUTPLL(MPLL_CNTL, 0x0400a403);
2271 	OUTPLL(SPLL_CNTL, 0x0400a433);
2274 	OUTPLL(M_SPLL_REF_FB_DIV, tmp);
2276 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
2286 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
2289 	OUTPLL(MPLL_CNTL, tmp & ~0x2);
2292 	OUTPLL(MPLL_CNTL, tmp & ~0x1);
2295 	OUTPLL(MCLK_CNTL, 0xaa3f1212);
2309 	OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
2312 	OUTPLL(SPLL_CNTL, tmp & ~0x1);
2315 	OUTPLL(SPLL_CNTL, tmp & ~0x2);
2319 	OUTPLL(SCLK_CNTL, tmp | 2);
2327 	OUTPLL(pllMDLL_CKO, cko);
2330 	OUTPLL(pllMDLL_CKO, cko);
2334 	OUTPLL(pllMDLL_RDCKA, cka);
2337 	OUTPLL(pllMDLL_RDCKA, cka);
2341 	OUTPLL(pllMDLL_RDCKB, ckb);
2344 	OUTPLL(pllMDLL_RDCKB, ckb);
2358 	OUTPLL(pllHTOTAL_CNTL, 0);
2359 	OUTPLL(pllHTOTAL2_CNTL, 0);
2389 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2390 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2391 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2395 	OUTPLL(MCLK_MISC, tmp);
2398 	OUTPLL(SCLK_CNTL, tmp);
2406 	OUTPLL(VCLK_ECP_CNTL, tmp);
2409 	OUTPLL(PPLL_CNTL, tmp);
2454 	OUTPLL(PPLL_REF_DIV, tmp);
2468 	OUTPLL(PPLL_DIV_0, 0x48090);
2471 	OUTPLL(PPLL_CNTL, tmp & ~0x2);
2474 	OUTPLL(PPLL_CNTL, tmp & ~0x1);
2478 	OUTPLL(VCLK_ECP_CNTL, tmp | 3);
2482 	OUTPLL(VCLK_ECP_CNTL, tmp);
2584 				OUTPLL( pllMDLL_CKO, tmp );  in radeon_set_suspend()