309 		OUTREG(CLOCK_CNTL_INDEX, tmp);  in radeon_pll_errata_after_data_slow()
311 		OUTREG(CLOCK_CNTL_INDEX, save);  in radeon_pll_errata_after_data_slow()
324 	OUTREG(addr, tmp);  in _OUTREGP()
343 	OUTREG(CLOCK_CNTL_DATA, val);  in __OUTPLL()
435 	OUTREG(MPP_TB_CONFIG, temp);  in radeon_map_ROM()
969 	OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +  in radeonfb_pan_display()
1009 			OUTREG(LVDS_GEN_CNTL, tmp);  in radeonfb_ioctl()
1023 			OUTREG(CRTC_EXT_CNTL, tmp);  in radeonfb_ioctl()
1079 	OUTREG(CRTC_EXT_CNTL, val);  in radeon_screen_blank()
1101 				OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
1103 				OUTREG(LVDS_GEN_CNTL, target_val  in radeon_screen_blank()
1110 					OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
1121 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1134 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1137 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1204 		                OUTREG(PALETTE_INDEX, pindex>>1);  in radeon_setcolreg()
1205 	       	         	OUTREG(PALETTE_DATA,  in radeon_setcolreg()
1214 			OUTREG(PALETTE_INDEX, pindex);  in radeon_setcolreg()
1215 			OUTREG(PALETTE_DATA, (red << 16) |  in radeon_setcolreg()
1259 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcolreg()
1289 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcmap()
1459 	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);  in radeon_lvds_timer_func()
1480 		OUTREG(common_regs[i].reg, common_regs[i].val);  in radeon_write_mode()
1484 		OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);  in radeon_write_mode()
1485 		OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);  in radeon_write_mode()
1486 		OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);  in radeon_write_mode()
1489 	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);  in radeon_write_mode()
1492 	OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);  in radeon_write_mode()
1494 	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);  in radeon_write_mode()
1495 	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);  in radeon_write_mode()
1496 	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);  in radeon_write_mode()
1497 	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);  in radeon_write_mode()
1498 	OUTREG(CRTC_OFFSET, 0);  in radeon_write_mode()
1499 	OUTREG(CRTC_OFFSET_CNTL, 0);  in radeon_write_mode()
1500 	OUTREG(CRTC_PITCH, mode->crtc_pitch);  in radeon_write_mode()
1501 	OUTREG(SURFACE_CNTL, mode->surface_cntl);  in radeon_write_mode()
1507 		OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);  in radeon_write_mode()
1508 		OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);  in radeon_write_mode()
1509 		OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);  in radeon_write_mode()
1510 		OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);  in radeon_write_mode()
1511 		OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);  in radeon_write_mode()
1512 		OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);  in radeon_write_mode()
1513 		OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);  in radeon_write_mode()
1514 		OUTREG(TMDS_CRC, mode->tmds_crc);  in radeon_write_mode()
1515 		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);  in radeon_write_mode()
2043 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);  in fixup_memory_mappings()
2048 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);  in fixup_memory_mappings()
2049 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);  in fixup_memory_mappings()
2057 	OUTREG(MC_FB_LOCATION,   in fixup_memory_mappings()
2061 	OUTREG(MC_FB_LOCATION, 0x7fff0000);  in fixup_memory_mappings()
2073 	OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));  in fixup_memory_mappings()
2075 	OUTREG(MC_AGP_LOCATION, 0xffffe000);  in fixup_memory_mappings()
2082 	OUTREG(DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2084 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2085 	OUTREG(OV0_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2087 	OUTREG(DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
2089 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
2090 	OUTREG(OV0_BASE_ADDR, 0);  in fixup_memory_mappings()
2095 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);  in fixup_memory_mappings()
2096 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);  in fixup_memory_mappings()
2098 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);	  in fixup_memory_mappings()
2123           OUTREG(MC_FB_LOCATION, tom);  in radeon_identify_vram()
2124           OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2125           OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2126           OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2129           OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);  in radeon_identify_vram()