Lines Matching refs:TUSB_SYS_REG_BASE
22 #define TUSB_SYS_REG_BASE 0x800 macro
24 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
30 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
31 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
55 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
67 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
70 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
73 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
78 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
95 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
96 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
97 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
113 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
114 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
115 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
116 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
117 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
118 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
119 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
120 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
121 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
122 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
123 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
124 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
125 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
126 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
127 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
128 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
131 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
132 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
133 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
134 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
171 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
172 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
173 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
174 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
175 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
176 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
183 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
184 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
185 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
203 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
204 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)