50 	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;  in tusb_get_revision()
52 		die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,  in tusb_get_revision()
70 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
71 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
73 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
74 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
76 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
77 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
79 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
80 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
82 		TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),  in tusb_print_revision()
101 		phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_wbus_quirk()
102 		phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_wbus_quirk()
110 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
111 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
112 	} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)  in tusb_wbus_quirk()
119 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
120 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
206 			val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
214 		val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
301 					val = musb_readl(fifo, 0);  in tusb_read_fifo()
343 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_draw_power()
366 	reg = musb_readl(tbase, TUSB_PRCM_CONF);  in tusb_set_clock_source()
407 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_allow_idle()
431 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
432 	prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_vbus_status()
442 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
561 	prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_set_vbus()
562 	conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_vbus()
579 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_vbus()
615 		musb_readl(tbase, TUSB_DEV_OTG_STAT),  in tusb_musb_set_vbus()
631 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
632 	phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_set_mode()
633 	phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_set_mode()
634 	dev_conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_mode()
666 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
678 	u32		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_otg_ints()
827 	int_mask = musb_readl(tbase, TUSB_INT_MASK);  in tusb_musb_interrupt()
830 	int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;  in tusb_musb_interrupt()
849 			reg = musb_readl(tbase, TUSB_SCRATCH_PAD);  in tusb_musb_interrupt()
858 		reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);  in tusb_musb_interrupt()
884 		u32	dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);  in tusb_musb_interrupt()
892 		u32	musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);  in tusb_musb_interrupt()
953 	if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)  in tusb_musb_enable()
1036 	if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=  in tusb_musb_start()
1069 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_start()
1073 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_start()