493 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in ep0_rxstate()
549 		musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in ep0_txstate()
614 		musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;  in musb_read_setup()
616 		musb->ep0_state = MUSB_EP0_STAGE_TX;  in musb_read_setup()
623 		musb->ep0_state = MUSB_EP0_STAGE_RX;  in musb_read_setup()
658 			csr, len, decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
673 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
682 		switch (musb->ep0_state) {  in musb_g_ep0_irq()
684 			musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;  in musb_g_ep0_irq()
687 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_irq()
691 			    decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
701 	switch (musb->ep0_state) {  in musb_g_ep0_irq()
762 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
773 		musb->ep0_state = MUSB_EP0_STAGE_SETUP;  in musb_g_ep0_irq()
802 			switch (musb->ep0_state) {  in musb_g_ep0_irq()
823 					musb->ep0_state =  in musb_g_ep0_irq()
836 					musb->ep0_state =  in musb_g_ep0_irq()
848 				decode_ep0stage(musb->ep0_state));  in musb_g_ep0_irq()
865 				musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
885 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_irq()
936 	switch (musb->ep0_state) {  in musb_g_ep0_queue()
944 				musb->ep0_state);  in musb_g_ep0_queue()
959 	if (musb->ep0_state == MUSB_EP0_STAGE_TX)  in musb_g_ep0_queue()
963 	else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {  in musb_g_ep0_queue()
967 			musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;  in musb_g_ep0_queue()
1022 	switch (musb->ep0_state) {  in musb_g_ep0_halt()
1041 		musb->ep0_state = MUSB_EP0_STAGE_IDLE;  in musb_g_ep0_halt()
1045 		musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);  in musb_g_ep0_halt()