Lines Matching refs:MUSB_CSR0
512 musb_writew(regs, MUSB_CSR0, csr); in ep0_rxstate()
532 musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0)); in ep0_txstate()
569 musb_writew(regs, MUSB_CSR0, csr); in ep0_txstate()
617 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY); in musb_read_setup()
618 while ((musb_readw(regs, MUSB_CSR0) in musb_read_setup()
654 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
670 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
674 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
679 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); in musb_g_ep0_irq()
693 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
867 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
884 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); in musb_g_ep0_irq()
968 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_queue()
979 musb_writew(regs, MUSB_CSR0, musb->ackpend); in musb_g_ep0_queue()
1030 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_halt()
1040 musb_writew(regs, MUSB_CSR0, csr); in musb_g_ep0_halt()