Lines Matching refs:BIT_ULL
1805 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1806 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1807 #define XHCI_NEC_HOST BIT_ULL(2)
1808 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1809 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1819 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1820 #define XHCI_BROKEN_MSI BIT_ULL(6)
1821 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1822 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1823 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1824 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1825 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1826 #define XHCI_INTEL_HOST BIT_ULL(12)
1827 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1828 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1829 #define XHCI_AVOID_BEI BIT_ULL(15)
1830 #define XHCI_PLAT BIT_ULL(16)
1831 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1832 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1834 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1835 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1836 #define XHCI_MTK_HOST BIT_ULL(21)
1837 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1838 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1839 #define XHCI_MISSING_CAS BIT_ULL(24)
1841 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1842 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1843 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1844 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1845 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1846 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1847 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1848 #define XHCI_ZERO_64B_REGS BIT_ULL(32)