Lines Matching refs:temp
59 u32 temp; in xhci_create_usb3_bos_desc() local
90 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
91 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
96 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
97 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
98 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
163 u16 temp; in xhci_common_hub_descriptor() local
169 temp = 0; in xhci_common_hub_descriptor()
172 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
174 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
177 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
180 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
188 u16 temp; in xhci_usb2_hub_descriptor() local
198 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
199 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
563 u32 temp; in xhci_set_port_power() local
567 temp = readl(port->addr); in xhci_set_port_power()
568 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
571 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
572 temp = readl(port->addr); in xhci_set_port_power()
574 index, temp); in xhci_set_port_power()
577 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
581 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
583 if (temp) in xhci_set_port_power()
592 u32 temp; in xhci_port_set_test_mode() local
597 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
598 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
599 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
668 u32 temp; in xhci_set_link_state() local
670 temp = readl(port->addr); in xhci_set_link_state()
671 temp = xhci_port_state_to_neutral(temp); in xhci_set_link_state()
672 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
673 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
674 writel(temp, port->addr); in xhci_set_link_state()
680 u32 temp; in xhci_set_remote_wake_mask() local
682 temp = readl(port->addr); in xhci_set_remote_wake_mask()
683 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
686 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
688 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
691 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
693 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
696 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
698 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
700 writel(temp, port->addr); in xhci_set_remote_wake_mask()
707 u32 temp; in xhci_test_and_clear_bit() local
709 temp = readl(port->addr); in xhci_test_and_clear_bit()
710 if (temp & port_bit) { in xhci_test_and_clear_bit()
711 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
712 temp |= port_bit; in xhci_test_and_clear_bit()
713 writel(temp, port->addr); in xhci_test_and_clear_bit()
1017 u32 temp, status; in xhci_hub_control() local
1068 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1069 if (temp == ~(u32)0) { in xhci_hub_control()
1074 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1075 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1081 wIndex, temp); in xhci_hub_control()
1095 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1112 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1113 if (temp == ~(u32)0) { in xhci_hub_control()
1118 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1122 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1123 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1135 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1136 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1137 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1159 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1163 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1167 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1172 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1175 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1176 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1185 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1209 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1219 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1223 if (!(temp & PORT_PE)) { in xhci_hub_control()
1252 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1266 temp = (temp | PORT_RESET); in xhci_hub_control()
1267 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1269 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1270 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); in xhci_hub_control()
1275 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1278 wIndex, temp); in xhci_hub_control()
1281 temp |= PORT_WR; in xhci_hub_control()
1282 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1283 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1288 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1289 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1290 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1291 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1296 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1297 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1298 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1299 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1314 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1320 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1321 if (temp == ~(u32)0) { in xhci_hub_control()
1327 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1330 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1332 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1333 if (temp & PORT_RESET) in xhci_hub_control()
1335 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1336 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1370 ports[wIndex]->addr, temp); in xhci_hub_control()
1374 ports[wIndex]->addr, temp); in xhci_hub_control()
1406 u32 temp, status; in xhci_hub_status_data() local
1436 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1437 if (temp == ~(u32)0) { in xhci_hub_status_data()
1442 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1444 if ((temp & mask) != 0 || in xhci_hub_status_data()
1451 if ((temp & PORT_RC)) in xhci_hub_status_data()
1581 u32 temp, portsc; in xhci_bus_resume() local
1600 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1601 temp &= ~CMD_EIE; in xhci_bus_resume()
1602 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1678 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1679 temp |= CMD_EIE; in xhci_bus_resume()
1680 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1681 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()