217 #define u132_write_pcimem(u132, member, data) \  macro
1533 	retval = u132_write_pcimem(u132, fminterval,  in u132_periodic_reinit()
1537 	return u132_write_pcimem(u132, periodicstart,  in u132_periodic_reinit()
1562 	retval = u132_write_pcimem(u132, intrdisable, OHCI_INTR_MIE);  in u132_init()
1633 	retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1646 			retval = u132_write_pcimem(u132,  in u132_run()
1659 	retval = u132_write_pcimem(u132, cmdstatus, OHCI_HCR);  in u132_run()
1678 		retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1685 	retval = u132_write_pcimem(u132, ed_controlhead, 0x00000000);  in u132_run()
1688 	retval = u132_write_pcimem(u132, ed_bulkhead, 0x11000000);  in u132_run()
1691 	retval = u132_write_pcimem(u132, hcca, 0x00000000);  in u132_run()
1713 	retval = u132_write_pcimem(u132, control, u132->hc_control);  in u132_run()
1716 	retval = u132_write_pcimem(u132, cmdstatus, OHCI_BLF);  in u132_run()
1726 	retval = u132_write_pcimem(u132, roothub.status, RH_HS_DRWE);  in u132_run()
1729 	retval = u132_write_pcimem(u132, intrstatus, mask);  in u132_run()
1732 	retval = u132_write_pcimem(u132, intrdisable,  in u132_run()
1745 		retval = u132_write_pcimem(u132, roothub.a, roothub_a);  in u132_run()
1750 		retval = u132_write_pcimem(u132, roothub.a, roothub_a);  in u132_run()
1754 	retval = u132_write_pcimem(u132, roothub.status, RH_HS_LPSC);  in u132_run()
1757 	retval = u132_write_pcimem(u132, roothub.b,  in u132_run()
2662 				retval = u132_write_pcimem(u132,  in u132_roothub_portreset()
2671 		retval = u132_write_pcimem(u132, roothub.portstatus[port_index],  in u132_roothub_portreset()
2695 			return u132_write_pcimem(u132,  in u132_roothub_setportfeature()
2698 			return u132_write_pcimem(u132,  in u132_roothub_setportfeature()
2751 		return u132_write_pcimem(u132, roothub.portstatus[port_index],  in u132_roothub_clearportfeature()