197 				dev->int_enable &= ~(INT_MSTWREND  in ep_reset()
200 				dev->int_enable &= ~INT_MSTRDEND;  in ep_reset()
201 			dev->int_enable &= ~INT_EPxDATASET (ep->num);  in ep_reset()
203 			dev->int_enable &= ~INT_EP0;  in ep_reset()
204 		writel(dev->int_enable, &regs->int_enable);  in ep_reset()
205 		readl(&regs->int_enable);  in ep_reset()
503 	dev->int_enable |= INT_EPxDATASET (epnum);  in pio_irq_enable()
504 	writel(dev->int_enable, &regs->int_enable);  in pio_irq_enable()
512 	dev->int_enable &= ~INT_EPxDATASET (epnum);  in pio_irq_disable()
513 	writel(dev->int_enable, &regs->int_enable);  in pio_irq_disable()
560 		ep->dev->int_enable |= INT_MSTRDEND;  in start_dma()
579 		ep->dev->int_enable |= INT_MSTWREND|INT_MSTWRTMOUT;  in start_dma()
583 	writel(ep->dev->int_enable, &regs->int_enable);  in start_dma()
598 			dev->int_enable &= ~INT_MSTRDEND;  in dma_advance()
600 			dev->int_enable &= ~(INT_MSTWREND|INT_MSTWRTMOUT);  in dma_advance()
601 		writel(dev->int_enable, &regs->int_enable);  in dma_advance()
781 			&& !(dev->int_enable & INT_EPxDATASET (ep->num)))  in goku_queue()
1160 	dump_intmask(m, "int_enable", readl(&regs->int_enable));  in udc_proc_read()
1295 	writel(0, &regs->int_enable);  in udc_reset()
1296 	readl(&regs->int_enable);  in udc_reset()
1297 	dev->int_enable = 0;  in udc_reset()
1304 	readl(&regs->int_enable);  in udc_reset()
1335 	dev->int_enable = INT_DEVWIDE | INT_EP0;  in ep0_start()
1336 	writel(dev->int_enable, &dev->regs->int_enable);  in ep0_start()
1337 	readl(&regs->int_enable);  in ep0_start()
1349 		dev->int_enable = INT_PWRDETECT;  in udc_enable()
1350 		writel(dev->int_enable, &dev->regs->int_enable);  in udc_enable()
1542 	stat = readl(&regs->int_status) & dev->int_enable;  in goku_irq()
1568 				dev->int_enable = INT_DEVWIDE;  in goku_irq()
1569 				writel(dev->int_enable, &dev->regs->int_enable);  in goku_irq()
1685 	(void)readl(&regs->int_enable);  in goku_irq()
1689 				readl(&regs->int_status), dev->int_enable);  in goku_irq()