Lines Matching refs:ep0_state
181 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_stall()
640 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_init()
793 && (udc->ep0_state == WAIT_FOR_SETUP)) { in ep0_setup_handle()
831 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep0_rx()
1098 if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP)) in qe_ep_tx()
1245 udc->ep0_state = DATA_STATE_NEED_ZLP; in ep0_prime_status()
1250 udc->ep0_state = WAIT_FOR_OUT_STATUS; in ep0_prime_status()
1262 switch (udc->ep0_state) { in ep0_req_complete()
1272 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1284 udc->ep0_state = WAIT_FOR_SETUP; in ep0_req_complete()
1304 ep->udc->ep0_state = WAIT_FOR_SETUP; in ep0_txcomplete()
1743 udc->ep0_state = DATA_STATE_XMIT; in __qe_ep_queue()
1745 udc->ep0_state = DATA_STATE_RECV; in __qe_ep_queue()
1832 udc->ep0_state = WAIT_FOR_SETUP; in qe_ep_set_halt()
2065 udc->ep0_state = DATA_STATE_XMIT; in setup_received_handle()
2068 udc->ep0_state = DATA_STATE_RECV; in setup_received_handle()
2084 udc->ep0_state = DATA_STATE_NEED_ZLP; in setup_received_handle()
2142 udc->ep0_state = WAIT_FOR_SETUP; in reset_irq()
2290 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_start()
2309 udc->ep0_state = WAIT_FOR_SETUP; in fsl_qe_stop()