99 	struct ci_hdrc				*ci;  member
259 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)  in ci_role()  argument
261 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);  in ci_role()
262 	return ci->roles[ci->role];  in ci_role()
265 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)  in ci_role_start()  argument
272 	if (!ci->roles[role])  in ci_role_start()
275 	ret = ci->roles[role]->start(ci);  in ci_role_start()
277 		ci->role = role;  in ci_role_start()
281 static inline void ci_role_stop(struct ci_hdrc *ci)  in ci_role_stop()  argument
283 	enum ci_role role = ci->role;  in ci_role_stop()
288 	ci->role = CI_ROLE_END;  in ci_role_stop()
290 	ci->roles[role]->stop(ci);  in ci_role_stop()
301 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)  in hw_read_id_reg()  argument
303 	return ioread32(ci->hw_bank.abs + offset) & mask;  in hw_read_id_reg()
313 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,  in hw_write_id_reg()  argument
317 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)  in hw_write_id_reg()
320 	iowrite32(data, ci->hw_bank.abs + offset);  in hw_write_id_reg()
331 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)  in hw_read()  argument
333 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
347 static inline void __hw_write(struct ci_hdrc *ci, u32 val,  in __hw_write()  argument
350 	if (ci->imx28_write_fix)  in __hw_write()
363 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_write()  argument
367 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
370 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);  in hw_write()
381 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_clear()  argument
384 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
386 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);  in hw_test_and_clear()
399 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,  in hw_test_and_write()  argument
402 	u32 val = hw_read(ci, reg, ~0);  in hw_test_and_write()
404 	hw_write(ci, reg, mask, data);  in hw_test_and_write()
414 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)  in ci_otg_is_fsm_mode()  argument
417 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;  in ci_otg_is_fsm_mode()
419 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&  in ci_otg_is_fsm_mode()
420 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||  in ci_otg_is_fsm_mode()
427 int ci_ulpi_init(struct ci_hdrc *ci);
428 void ci_ulpi_exit(struct ci_hdrc *ci);
429 int ci_ulpi_resume(struct ci_hdrc *ci);
431 u32 hw_read_intr_enable(struct ci_hdrc *ci);
433 u32 hw_read_intr_status(struct ci_hdrc *ci);
435 int hw_device_reset(struct ci_hdrc *ci);
437 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
439 u8 hw_port_test_get(struct ci_hdrc *ci);
441 void hw_phymode_configure(struct ci_hdrc *ci);
443 void ci_platform_configure(struct ci_hdrc *ci);
445 void dbg_create_files(struct ci_hdrc *ci);
447 void dbg_remove_files(struct ci_hdrc *ci);