1499 	unsigned char RegValue;  in set_break()  local
1511 	RegValue = read_reg(info, CTL);  in set_break()
1513 		RegValue |= BIT3;  in set_break()
1515 		RegValue &= ~BIT3;  in set_break()
1516 	write_reg(info, CTL, RegValue);  in set_break()
4365   	unsigned char RegValue;  in async_mode()  local
4380 	RegValue = 0x00;  in async_mode()
4382 		RegValue |= BIT1;  in async_mode()
4383 	write_reg(info, MD0, RegValue);  in async_mode()
4394 	RegValue = 0x40;  in async_mode()
4396 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4397 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4398 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4401 		RegValue |= BIT1;  in async_mode()
4403 			RegValue |= BIT0;  in async_mode()
4405 	write_reg(info, MD1, RegValue);  in async_mode()
4414 	RegValue = 0x00;  in async_mode()
4416 		RegValue |= (BIT1 + BIT0);  in async_mode()
4417 	write_reg(info, MD2, RegValue);  in async_mode()
4425 	RegValue=BIT6;  in async_mode()
4426 	write_reg(info, RXS, RegValue);  in async_mode()
4434 	RegValue=BIT6;  in async_mode()
4435 	write_reg(info, TXS, RegValue);  in async_mode()
4479 	RegValue = 0x10;  in async_mode()
4481 		RegValue |= 0x01;  in async_mode()
4482 	write_reg(info, CTL, RegValue);  in async_mode()
4503 	unsigned char RegValue;  in hdlc_mode()  local
4527 	RegValue = 0x81;  in hdlc_mode()
4529 		RegValue |= BIT4;  in hdlc_mode()
4531 		RegValue |= BIT4;  in hdlc_mode()
4533 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4534 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4545 	RegValue = 0x00;  in hdlc_mode()
4546 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4558 	RegValue = 0x00;  in hdlc_mode()
4560 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4561 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4562 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4563 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4572 		RegValue |= BIT3;  in hdlc_mode()
4577 		RegValue |= BIT4;  in hdlc_mode()
4579 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4588 	RegValue=0;  in hdlc_mode()
4590 		RegValue |= BIT6;  in hdlc_mode()
4592 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4593 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4601 	RegValue=0;  in hdlc_mode()
4603 		RegValue |= BIT6;  in hdlc_mode()
4605 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4606 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4684 	RegValue = 0x10;  in hdlc_mode()
4686 		RegValue |= 0x01;  in hdlc_mode()
4687 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4705 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4709 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4710 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4711 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4712 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4713 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4714 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4715 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4718 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4754 	unsigned char RegValue;  in set_signals()  local
4757 	RegValue = read_reg(info, CTL);  in set_signals()
4759 		RegValue &= ~BIT0;  in set_signals()
4761 		RegValue |= BIT0;  in set_signals()
4762 	write_reg(info, CTL, RegValue);  in set_signals()