427 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
434 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1399 	wr_reg16(info, TCR, value);  in set_break()
2138 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2278 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2279 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2715 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2768 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2831 			wr_reg16(info, SCR,  in wait_mgsl_event()
2867 	wr_reg16(info, TCR, val);  in set_interface()
3852 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3904 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3943 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3953 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3954 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3959 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3974 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
3978 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
3979 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
3986 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
3994 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
4010 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
4019 		wr_reg16(info, TCR,  in tx_start()
4040 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
4045 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
4064 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
4069 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4150 	wr_reg16(info, TCR, val);  in async_mode()
4187 	wr_reg16(info, RCR, val);  in async_mode()
4233 	wr_reg16(info, SCR, val);  in async_mode()
4312 	wr_reg16(info, TCR, val);  in sync_mode()
4375 	wr_reg16(info, RCR, val);  in sync_mode()
4426 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4457 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4484 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4945 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4946 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4973 	wr_reg16(info, TCR,  in irq_test()
4977 	wr_reg16(info, TDR, 0);  in irq_test()