Lines Matching refs:usc_InDmaReg
639 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
664 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
1600 status = usc_InDmaReg( info, RDMR ); in mgsl_isr_receive_dma()
1645 status = usc_InDmaReg( info, TDMR ); in mgsl_isr_transmit_dma()
1693 DmaVector = usc_InDmaReg(info, DIVR); in mgsl_interrupt()
3505 u16 Tdmr = usc_InDmaReg( info, TDMR ); in line_info()
3508 u16 Rdmr = usc_InDmaReg( info, RDMR ); in line_info()
4535 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) in usc_InDmaReg() function
5112 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */ in usc_set_sdlc_mode()
5113 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */ in usc_set_sdlc_mode()
5414 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_process_rxoverrun_sync()
5503 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); in usc_start_receiver()
5609 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); in usc_start_transmitter()
6938 (usc_InDmaReg( info, DIVR ) != 0) ){ in mgsl_register_test()
6959 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ in mgsl_register_test()
7132 usc_InDmaReg( info, RDMR ); in mgsl_dma_test()
7155 status = usc_InDmaReg( info, RDMR ); in mgsl_dma_test()