Lines Matching refs:RegValue
4506 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutDmaReg() argument
4512 outw( RegValue, info->io_base ); in usc_OutDmaReg()
4562 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() argument
4565 outw( RegValue, info->io_base + CCAR ); in usc_OutReg()
4603 u16 RegValue; in usc_set_sdlc_mode() local
4616 RegValue=usc_InReg(info,TMDR); in usc_set_sdlc_mode()
4617 PreSL1660 = (RegValue == IUSC_PRE_SL1660); in usc_set_sdlc_mode()
4633 RegValue = 0x8e06; in usc_set_sdlc_mode()
4654 RegValue = 0x0001; /* Set Receive mode = external sync */ in usc_set_sdlc_mode()
4671 RegValue |= 0x0400; in usc_set_sdlc_mode()
4675 RegValue = 0x0606; in usc_set_sdlc_mode()
4678 RegValue |= BIT14; in usc_set_sdlc_mode()
4680 RegValue |= BIT15; in usc_set_sdlc_mode()
4682 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4686 RegValue |= BIT13; in usc_set_sdlc_mode()
4691 RegValue |= BIT12; in usc_set_sdlc_mode()
4697 RegValue |= BIT4; in usc_set_sdlc_mode()
4700 usc_OutReg( info, CMR, RegValue ); in usc_set_sdlc_mode()
4701 info->cmr_value = RegValue; in usc_set_sdlc_mode()
4718 RegValue = 0x0500; in usc_set_sdlc_mode()
4721 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4722 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4723 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4724 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4725 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4726 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4727 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4731 RegValue |= BIT9; in usc_set_sdlc_mode()
4733 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4735 usc_OutReg( info, RMR, RegValue ); in usc_set_sdlc_mode()
4766 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4769 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4771 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); in usc_set_sdlc_mode()
4793 RegValue = 0x0400; in usc_set_sdlc_mode()
4796 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4797 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4798 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4799 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4800 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4801 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4802 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4806 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4808 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4810 usc_OutReg( info, TMR, RegValue ); in usc_set_sdlc_mode()
4877 RegValue = 0x0f40; in usc_set_sdlc_mode()
4880 RegValue |= 0x0003; /* RxCLK from DPLL */ in usc_set_sdlc_mode()
4882 RegValue |= 0x0004; /* RxCLK from BRG0 */ in usc_set_sdlc_mode()
4884 RegValue |= 0x0006; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4886 RegValue |= 0x0007; /* RxCLK from Port1 */ in usc_set_sdlc_mode()
4889 RegValue |= 0x0018; /* TxCLK from DPLL */ in usc_set_sdlc_mode()
4891 RegValue |= 0x0020; /* TxCLK from BRG0 */ in usc_set_sdlc_mode()
4893 RegValue |= 0x0038; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4895 RegValue |= 0x0030; /* TxCLK from Port0 */ in usc_set_sdlc_mode()
4897 usc_OutReg( info, CMCR, RegValue ); in usc_set_sdlc_mode()
4915 RegValue = 0x0000; in usc_set_sdlc_mode()
4932 RegValue |= BIT10; in usc_set_sdlc_mode()
4936 RegValue |= BIT11; in usc_set_sdlc_mode()
4969 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
4975 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
4977 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
4979 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
4983 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
5130 RegValue = 0x8080; in usc_set_sdlc_mode()
5133 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()
5134 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()
5135 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
5139 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; in usc_set_sdlc_mode()
5140 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5141 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; in usc_set_sdlc_mode()
5142 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
5145 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
5842 u16 RegValue; in usc_set_async_mode() local
5864 RegValue = 0; in usc_set_async_mode()
5866 RegValue |= BIT14; in usc_set_async_mode()
5867 usc_OutReg( info, CMR, RegValue ); in usc_set_async_mode()
5882 RegValue = 0; in usc_set_async_mode()
5885 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5888 RegValue |= BIT5; in usc_set_async_mode()
5890 RegValue |= BIT6; in usc_set_async_mode()
5893 usc_OutReg( info, RMR, RegValue ); in usc_set_async_mode()
5939 RegValue = 0; in usc_set_async_mode()
5942 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5945 RegValue |= BIT5; in usc_set_async_mode()
5947 RegValue |= BIT6; in usc_set_async_mode()
5950 usc_OutReg( info, TMR, RegValue ); in usc_set_async_mode()