Lines Matching refs:BIT15
557 #define MISCSTATUS_RXC_LATCHED BIT15
577 #define SICR_RXC_ACTIVE BIT15
579 #define SICR_RXC (BIT15|BIT14)
634 #define DICR_MASTER BIT15
1839 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); in shutdown()
4680 RegValue |= BIT15; in usc_set_sdlc_mode()
4682 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4724 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4725 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4726 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4727 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4799 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4800 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4801 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4802 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
5032 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14)); in usc_set_sdlc_mode()