65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,  in stm32_config_reg_rs485()  argument
73 	over8 = *cr1 & USART_CR1_OVER8;  in stm32_config_reg_rs485()
85 	*cr1 |= rs485_deat_dedt;  in stm32_config_reg_rs485()
97 	*cr1 |= rs485_deat_dedt;  in stm32_config_reg_rs485()
106 	u32 usartdiv, baud, cr1, cr3;  in stm32_config_rs485()  local
111 	stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_config_rs485()
118 		cr1 = readl_relaxed(port->membase + ofs->cr1);  in stm32_config_rs485()
122 		over8 = cr1 & USART_CR1_OVER8;  in stm32_config_rs485()
129 		stm32_config_reg_rs485(&cr1, &cr3,  in stm32_config_rs485()
142 		writel_relaxed(cr1, port->membase + ofs->cr1);  in stm32_config_rs485()
145 		stm32_clr_bits(port, ofs->cr1,  in stm32_config_rs485()
149 	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_config_rs485()
318 	stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);  in stm32_transmit_chars_pio()
501 	stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);  in stm32_stop_tx()
523 	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);  in stm32_throttle()
535 	stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);  in stm32_unthrottle()
545 	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);  in stm32_stop_rx()
580 	stm32_set_bits(port, ofs->cr1, val);  in stm32_startup()
596 	stm32_clr_bits(port, ofs->cr1, val);  in stm32_shutdown()
612 	u32 cr1, cr2, cr3;  in stm32_set_termios()  local
623 	writel_relaxed(0, port->membase + ofs->cr1);  in stm32_set_termios()
625 	cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;  in stm32_set_termios()
628 		cr1 |= USART_CR1_FIFOEN;  in stm32_set_termios()
636 		cr1 |= USART_CR1_PCE;  in stm32_set_termios()
639 				cr1 |= USART_CR1_M0;  in stm32_set_termios()
641 				cr1 |= USART_CR1_M;  in stm32_set_termios()
646 		cr1 |= USART_CR1_PS;  in stm32_set_termios()
664 		cr1 |= USART_CR1_OVER8;  in stm32_set_termios()
665 		stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);  in stm32_set_termios()
668 		cr1 &= ~USART_CR1_OVER8;  in stm32_set_termios()
669 		stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);  in stm32_set_termios()
706 		stm32_config_reg_rs485(&cr1, &cr3,  in stm32_set_termios()
719 		cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);  in stm32_set_termios()
724 	writel_relaxed(cr1, port->membase + ofs->cr1);  in stm32_set_termios()
726 	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_set_termios()
772 		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_pm()
1122 	old_cr1 = readl_relaxed(port->membase + ofs->cr1);  in stm32_console_write()
1125 	writel_relaxed(new_cr1, port->membase + ofs->cr1);  in stm32_console_write()
1130 	writel_relaxed(old_cr1, port->membase + ofs->cr1);  in stm32_console_write()
1202 		stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_serial_enable_wakeup()
1203 		stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);  in stm32_serial_enable_wakeup()
1209 		stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_serial_enable_wakeup()
1211 		stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);  in stm32_serial_enable_wakeup()