Lines Matching refs:tup
127 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
128 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
130 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup, in tegra_uart_read() argument
133 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
136 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val, in tegra_uart_write() argument
139 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
149 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_get_mctrl() local
160 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
165 static void set_rts(struct tegra_uart_port *tup, bool active) in set_rts() argument
169 mcr = tup->mcr_shadow; in set_rts()
174 if (mcr != tup->mcr_shadow) { in set_rts()
175 tegra_uart_write(tup, mcr, UART_MCR); in set_rts()
176 tup->mcr_shadow = mcr; in set_rts()
180 static void set_dtr(struct tegra_uart_port *tup, bool active) in set_dtr() argument
184 mcr = tup->mcr_shadow; in set_dtr()
189 if (mcr != tup->mcr_shadow) { in set_dtr()
190 tegra_uart_write(tup, mcr, UART_MCR); in set_dtr()
191 tup->mcr_shadow = mcr; in set_dtr()
197 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_mctrl() local
200 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
201 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
204 set_dtr(tup, dtr_enable); in tegra_uart_set_mctrl()
209 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_break_ctl() local
212 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
217 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_break_ctl()
218 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
230 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup, in tegra_uart_wait_cycle_time() argument
233 if (tup->current_baud) in tegra_uart_wait_cycle_time()
234 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup, in tegra_uart_wait_sym_time() argument
241 if (tup->current_baud) in tegra_uart_wait_sym_time()
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
243 tup->current_baud)); in tegra_uart_wait_sym_time()
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits) in tegra_uart_fifo_reset() argument
248 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
252 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
255 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
258 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
260 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
264 tegra_uart_read(tup, UART_SCR); in tegra_uart_fifo_reset()
271 tegra_uart_wait_cycle_time(tup, 32); in tegra_uart_fifo_reset()
274 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) in tegra_set_baudrate() argument
281 if (tup->current_baud == baud) in tegra_set_baudrate()
284 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
286 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
288 dev_err(tup->uport.dev, in tegra_set_baudrate()
294 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
298 lcr = tup->lcr_shadow; in tegra_set_baudrate()
300 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
302 tegra_uart_write(tup, divisor & 0xFF, UART_TX); in tegra_set_baudrate()
303 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER); in tegra_set_baudrate()
306 tegra_uart_write(tup, lcr, UART_LCR); in tegra_set_baudrate()
309 tegra_uart_read(tup, UART_SCR); in tegra_set_baudrate()
311 tup->current_baud = baud; in tegra_set_baudrate()
314 tegra_uart_wait_sym_time(tup, 2); in tegra_set_baudrate()
318 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, in tegra_uart_decode_rx_error() argument
327 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
328 dev_err(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
332 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
333 dev_err(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
336 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
337 dev_err(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
339 dev_err(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
340 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
343 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); in tegra_uart_decode_rx_error()
359 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes) in tegra_uart_fill_tx_fifo() argument
361 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
366 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
367 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_fill_tx_fifo()
371 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
373 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
377 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup, in tegra_uart_start_pio_tx() argument
383 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
384 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
385 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
386 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
391 struct tegra_uart_port *tup = args; in tegra_uart_tx_dma_complete() local
392 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
397 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
398 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
399 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
400 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
402 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
404 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
405 tegra_uart_start_next_tx(tup); in tegra_uart_tx_dma_complete()
406 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
409 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, in tegra_uart_start_tx_dma() argument
412 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
415 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_start_tx_dma()
418 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
419 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
420 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
421 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
423 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
424 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
428 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
429 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
430 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
431 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
432 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
433 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
437 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup) in tegra_uart_start_next_tx() argument
441 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
449 tegra_uart_start_pio_tx(tup, count); in tegra_uart_start_next_tx()
451 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail)); in tegra_uart_start_next_tx()
453 tegra_uart_start_tx_dma(tup, count); in tegra_uart_start_next_tx()
459 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_start_tx() local
462 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
463 tegra_uart_start_next_tx(tup); in tegra_uart_start_tx()
468 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_tx_empty() local
473 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
474 unsigned long lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_tx_empty()
484 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_tx() local
485 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_stop_tx()
489 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
492 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
493 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
494 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
495 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
497 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
500 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup) in tegra_uart_handle_tx_pio() argument
502 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
504 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
505 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
507 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
508 tegra_uart_start_next_tx(tup); in tegra_uart_handle_tx_pio()
511 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, in tegra_uart_handle_rx_pio() argument
519 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_handle_rx_pio()
523 flag = tegra_uart_decode_rx_error(tup, lsr); in tegra_uart_handle_rx_pio()
524 ch = (unsigned char) tegra_uart_read(tup, UART_RX); in tegra_uart_handle_rx_pio()
525 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
527 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty) in tegra_uart_handle_rx_pio()
532 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup, in tegra_uart_copy_rx_to_tty() argument
542 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
544 dev_err(tup->uport.dev, "No tty port\n"); in tegra_uart_copy_rx_to_tty()
547 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
550 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
553 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
555 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
559 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup, in tegra_uart_rx_buffer_push() argument
562 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
566 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
567 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
570 tegra_uart_copy_rx_to_tty(tup, port, count); in tegra_uart_rx_buffer_push()
572 tegra_uart_handle_rx_pio(tup, port); in tegra_uart_rx_buffer_push()
581 struct tegra_uart_port *tup = args; in tegra_uart_rx_dma_complete() local
582 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
589 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
592 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
597 if (tup->rts_active) in tegra_uart_rx_dma_complete()
598 set_rts(tup, false); in tegra_uart_rx_dma_complete()
600 tegra_uart_rx_buffer_push(tup, 0); in tegra_uart_rx_dma_complete()
601 tegra_uart_start_rx_dma(tup); in tegra_uart_rx_dma_complete()
604 if (tup->rts_active) in tegra_uart_rx_dma_complete()
605 set_rts(tup, true); in tegra_uart_rx_dma_complete()
611 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) in tegra_uart_handle_rx_dma() argument
616 if (tup->rts_active) in tegra_uart_handle_rx_dma()
617 set_rts(tup, false); in tegra_uart_handle_rx_dma()
619 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_handle_rx_dma()
620 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_handle_rx_dma()
621 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_handle_rx_dma()
622 tegra_uart_start_rx_dma(tup); in tegra_uart_handle_rx_dma()
624 if (tup->rts_active) in tegra_uart_handle_rx_dma()
625 set_rts(tup, true); in tegra_uart_handle_rx_dma()
628 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup) in tegra_uart_start_rx_dma() argument
632 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
633 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
635 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
636 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
640 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
641 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
642 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_start_rx_dma()
644 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
645 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
646 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
652 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_handle_modem_signal_change() local
655 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_handle_modem_signal_change()
660 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
662 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
665 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
668 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
673 struct tegra_uart_port *tup = data; in tegra_uart_isr() local
674 struct uart_port *u = &tup->uport; in tegra_uart_isr()
682 iir = tegra_uart_read(tup, UART_IIR); in tegra_uart_isr()
685 tegra_uart_handle_rx_dma(tup); in tegra_uart_isr()
686 if (tup->rx_in_progress) { in tegra_uart_isr()
687 ier = tup->ier_shadow; in tegra_uart_isr()
690 tup->ier_shadow = ier; in tegra_uart_isr()
691 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
704 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
705 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
706 tegra_uart_handle_tx_pio(tup); in tegra_uart_isr()
715 ier = tup->ier_shadow; in tegra_uart_isr()
717 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
720 tup->ier_shadow = ier; in tegra_uart_isr()
721 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_isr()
726 tegra_uart_decode_rx_error(tup, in tegra_uart_isr()
727 tegra_uart_read(tup, UART_LSR)); in tegra_uart_isr()
739 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_stop_rx() local
743 if (tup->rts_active) in tegra_uart_stop_rx()
744 set_rts(tup, false); in tegra_uart_stop_rx()
746 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
749 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */ in tegra_uart_stop_rx()
751 ier = tup->ier_shadow; in tegra_uart_stop_rx()
754 tup->ier_shadow = ier; in tegra_uart_stop_rx()
755 tegra_uart_write(tup, ier, UART_IER); in tegra_uart_stop_rx()
756 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
757 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_stop_rx()
758 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_stop_rx()
759 tegra_uart_rx_buffer_push(tup, state.residue); in tegra_uart_stop_rx()
762 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup) in tegra_uart_hw_deinit() argument
765 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
766 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
773 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_hw_deinit()
775 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
777 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
778 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
780 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
789 msr = tegra_uart_read(tup, UART_MSR); in tegra_uart_hw_deinit()
790 mcr = tegra_uart_read(tup, UART_MCR); in tegra_uart_hw_deinit()
793 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
797 lsr = tegra_uart_read(tup, UART_LSR); in tegra_uart_hw_deinit()
801 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
803 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); in tegra_uart_hw_deinit()
804 tup->current_baud = 0; in tegra_uart_hw_deinit()
805 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
807 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
810 static int tegra_uart_hw_init(struct tegra_uart_port *tup) in tegra_uart_hw_init() argument
814 tup->fcr_shadow = 0; in tegra_uart_hw_init()
815 tup->mcr_shadow = 0; in tegra_uart_hw_init()
816 tup->lcr_shadow = 0; in tegra_uart_hw_init()
817 tup->ier_shadow = 0; in tegra_uart_hw_init()
818 tup->current_baud = 0; in tegra_uart_hw_init()
820 clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
823 reset_control_assert(tup->rst); in tegra_uart_hw_init()
825 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
827 tup->rx_in_progress = 0; in tegra_uart_hw_init()
828 tup->tx_in_progress = 0; in tegra_uart_hw_init()
848 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
849 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
850 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
851 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
854 tegra_uart_read(tup, UART_SCR); in tegra_uart_hw_init()
861 tegra_uart_wait_cycle_time(tup, 3); in tegra_uart_hw_init()
868 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
869 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); in tegra_uart_hw_init()
870 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
871 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
873 ret = tegra_uart_start_rx_dma(tup); in tegra_uart_hw_init()
875 dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); in tegra_uart_hw_init()
878 tup->rx_in_progress = 1; in tegra_uart_hw_init()
898 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
899 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
903 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup, in tegra_uart_dma_channel_free() argument
907 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
908 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
909 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
910 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
911 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
912 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
913 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
915 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
916 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
917 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
919 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
920 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
921 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
925 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, in tegra_uart_dma_channel_allocate() argument
934 dma_chan = dma_request_slave_channel_reason(tup->uport.dev, in tegra_uart_dma_channel_allocate()
938 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
944 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
948 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
953 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
956 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
957 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
958 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
960 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
961 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
963 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
964 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
968 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
969 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
972 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
973 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
974 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
979 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
981 tegra_uart_dma_channel_free(tup, dma_to_memory); in tegra_uart_dma_channel_allocate()
990 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_startup() local
993 ret = tegra_uart_dma_channel_allocate(tup, false); in tegra_uart_startup()
999 ret = tegra_uart_dma_channel_allocate(tup, true); in tegra_uart_startup()
1005 ret = tegra_uart_hw_init(tup); in tegra_uart_startup()
1012 dev_name(u->dev), tup); in tegra_uart_startup()
1020 tegra_uart_dma_channel_free(tup, true); in tegra_uart_startup()
1022 tegra_uart_dma_channel_free(tup, false); in tegra_uart_startup()
1032 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_flush_buffer() local
1034 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1035 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1036 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1041 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_shutdown() local
1043 tegra_uart_hw_deinit(tup); in tegra_uart_shutdown()
1045 tup->rx_in_progress = 0; in tegra_uart_shutdown()
1046 tup->tx_in_progress = 0; in tegra_uart_shutdown()
1048 tegra_uart_dma_channel_free(tup, true); in tegra_uart_shutdown()
1049 tegra_uart_dma_channel_free(tup, false); in tegra_uart_shutdown()
1050 free_irq(u->irq, tup); in tegra_uart_shutdown()
1055 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_enable_ms() local
1057 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1058 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1059 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1066 struct tegra_uart_port *tup = to_tegra_uport(u); in tegra_uart_set_termios() local
1071 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1073 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1079 if (tup->rts_active) in tegra_uart_set_termios()
1080 set_rts(tup, false); in tegra_uart_set_termios()
1083 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1084 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1085 tegra_uart_write(tup, 0, UART_IER); in tegra_uart_set_termios()
1086 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1089 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1137 tegra_uart_write(tup, lcr, UART_LCR); in tegra_uart_set_termios()
1138 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1139 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1146 tegra_set_baudrate(tup, baud); in tegra_uart_set_termios()
1153 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1154 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1155 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1157 if (tup->rts_active) in tegra_uart_set_termios()
1158 set_rts(tup, true); in tegra_uart_set_termios()
1160 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1161 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1162 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1169 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1172 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1173 tegra_uart_read(tup, UART_IER); in tegra_uart_set_termios()
1210 struct tegra_uart_port *tup) in tegra_uart_parse_dt() argument
1220 tup->uport.line = port; in tegra_uart_parse_dt()
1222 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1253 struct tegra_uart_port *tup; in tegra_uart_probe() local
1267 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1268 if (!tup) { in tegra_uart_probe()
1273 ret = tegra_uart_parse_dt(pdev, tup); in tegra_uart_probe()
1277 u = &tup->uport; in tegra_uart_probe()
1282 tup->cdata = cdata; in tegra_uart_probe()
1284 platform_set_drvdata(pdev, tup); in tegra_uart_probe()
1296 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1297 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1299 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1302 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1303 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1305 return PTR_ERR(tup->rst); in tegra_uart_probe()
1326 struct tegra_uart_port *tup = platform_get_drvdata(pdev); in tegra_uart_remove() local
1327 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1336 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_suspend() local
1337 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1344 struct tegra_uart_port *tup = dev_get_drvdata(dev); in tegra_uart_resume() local
1345 struct uart_port *u = &tup->uport; in tegra_uart_resume()