Lines Matching refs:uap
91 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
92 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
93 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
116 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) in pmz_load_zsregs() argument
122 unsigned char stat = read_zsreg(uap, R1); in pmz_load_zsregs()
128 ZS_CLEARERR(uap); in pmz_load_zsregs()
129 zssync(uap); in pmz_load_zsregs()
130 ZS_CLEARFIFO(uap); in pmz_load_zsregs()
131 zssync(uap); in pmz_load_zsregs()
132 ZS_CLEARERR(uap); in pmz_load_zsregs()
135 write_zsreg(uap, R1, in pmz_load_zsregs()
139 write_zsreg(uap, R4, regs[R4]); in pmz_load_zsregs()
142 write_zsreg(uap, R10, regs[R10]); in pmz_load_zsregs()
145 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); in pmz_load_zsregs()
146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
149 write_zsreg(uap, R15, regs[R15] | EN85C30); in pmz_load_zsregs()
150 write_zsreg(uap, R7, regs[R7P]); in pmz_load_zsregs()
153 write_zsreg(uap, R15, regs[R15] & ~EN85C30); in pmz_load_zsregs()
156 write_zsreg(uap, R6, regs[R6]); in pmz_load_zsregs()
157 write_zsreg(uap, R7, regs[R7]); in pmz_load_zsregs()
160 write_zsreg(uap, R14, regs[R14] & ~BRENAB); in pmz_load_zsregs()
163 write_zsreg(uap, R11, regs[R11]); in pmz_load_zsregs()
166 write_zsreg(uap, R12, regs[R12]); in pmz_load_zsregs()
167 write_zsreg(uap, R13, regs[R13]); in pmz_load_zsregs()
170 write_zsreg(uap, R14, regs[R14]); in pmz_load_zsregs()
173 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
174 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
177 write_zsreg(uap, R3, regs[R3]); in pmz_load_zsregs()
178 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
181 write_zsreg(uap, R1, regs[R1]); in pmz_load_zsregs()
184 write_zsreg(uap, R9, regs[R9]); in pmz_load_zsregs()
195 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) in pmz_maybe_update_regs() argument
197 if (!ZS_REGS_HELD(uap)) { in pmz_maybe_update_regs()
198 if (ZS_TX_ACTIVE(uap)) { in pmz_maybe_update_regs()
199 uap->flags |= PMACZILOG_FLAG_REGS_HELD; in pmz_maybe_update_regs()
202 pmz_load_zsregs(uap, uap->curregs); in pmz_maybe_update_regs()
207 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) in pmz_interrupt_control() argument
210 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; in pmz_interrupt_control()
211 if (!ZS_IS_EXTCLK(uap)) in pmz_interrupt_control()
212 uap->curregs[1] |= EXT_INT_ENAB; in pmz_interrupt_control()
214 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in pmz_interrupt_control()
216 write_zsreg(uap, R1, uap->curregs[1]); in pmz_interrupt_control()
219 static bool pmz_receive_chars(struct uart_pmac_port *uap) in pmz_receive_chars() argument
226 if (uap->port.state == NULL) { in pmz_receive_chars()
228 (void)read_zsdata(uap); in pmz_receive_chars()
231 port = &uap->port.state->port; in pmz_receive_chars()
237 r1 = read_zsreg(uap, R1); in pmz_receive_chars()
238 ch = read_zsdata(uap); in pmz_receive_chars()
241 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
242 zssync(uap); in pmz_receive_chars()
245 ch &= uap->parity_mask; in pmz_receive_chars()
246 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { in pmz_receive_chars()
247 uap->flags &= ~PMACZILOG_FLAG_BREAK; in pmz_receive_chars()
254 uap->port.sysrq = jiffies + HZ*5; in pmz_receive_chars()
258 if (uap->port.sysrq) { in pmz_receive_chars()
260 spin_unlock(&uap->port.lock); in pmz_receive_chars()
261 swallow = uart_handle_sysrq_char(&uap->port, ch); in pmz_receive_chars()
262 spin_lock(&uap->port.lock); in pmz_receive_chars()
273 uap->port.icount.rx++; in pmz_receive_chars()
280 uap->port.icount.brk++; in pmz_receive_chars()
281 if (uart_handle_break(&uap->port)) in pmz_receive_chars()
285 uap->port.icount.parity++; in pmz_receive_chars()
287 uap->port.icount.frame++; in pmz_receive_chars()
289 uap->port.icount.overrun++; in pmz_receive_chars()
290 r1 &= uap->port.read_status_mask; in pmz_receive_chars()
299 if (uap->port.ignore_status_mask == 0xff || in pmz_receive_chars()
300 (r1 & uap->port.ignore_status_mask) == 0) { in pmz_receive_chars()
315 ch = read_zsreg(uap, R0); in pmz_receive_chars()
322 pmz_interrupt_control(uap, 0); in pmz_receive_chars()
327 static void pmz_status_handle(struct uart_pmac_port *uap) in pmz_status_handle() argument
331 status = read_zsreg(uap, R0); in pmz_status_handle()
332 write_zsreg(uap, R0, RES_EXT_INT); in pmz_status_handle()
333 zssync(uap); in pmz_status_handle()
335 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { in pmz_status_handle()
337 uap->port.icount.dsr++; in pmz_status_handle()
344 if ((status ^ uap->prev_status) & DCD) in pmz_status_handle()
345 uart_handle_dcd_change(&uap->port, in pmz_status_handle()
347 if ((status ^ uap->prev_status) & CTS) in pmz_status_handle()
348 uart_handle_cts_change(&uap->port, in pmz_status_handle()
351 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pmz_status_handle()
355 uap->flags |= PMACZILOG_FLAG_BREAK; in pmz_status_handle()
357 uap->prev_status = status; in pmz_status_handle()
360 static void pmz_transmit_chars(struct uart_pmac_port *uap) in pmz_transmit_chars() argument
364 if (ZS_IS_CONS(uap)) { in pmz_transmit_chars()
365 unsigned char status = read_zsreg(uap, R0); in pmz_transmit_chars()
379 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
381 if (ZS_REGS_HELD(uap)) { in pmz_transmit_chars()
382 pmz_load_zsregs(uap, uap->curregs); in pmz_transmit_chars()
383 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; in pmz_transmit_chars()
386 if (ZS_TX_STOPPED(uap)) { in pmz_transmit_chars()
387 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; in pmz_transmit_chars()
399 if (!ZS_IS_OPEN(uap)) in pmz_transmit_chars()
402 if (uap->port.x_char) { in pmz_transmit_chars()
403 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
404 write_zsdata(uap, uap->port.x_char); in pmz_transmit_chars()
405 zssync(uap); in pmz_transmit_chars()
406 uap->port.icount.tx++; in pmz_transmit_chars()
407 uap->port.x_char = 0; in pmz_transmit_chars()
411 if (uap->port.state == NULL) in pmz_transmit_chars()
413 xmit = &uap->port.state->xmit; in pmz_transmit_chars()
415 uart_write_wakeup(&uap->port); in pmz_transmit_chars()
418 if (uart_tx_stopped(&uap->port)) in pmz_transmit_chars()
421 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_transmit_chars()
422 write_zsdata(uap, xmit->buf[xmit->tail]); in pmz_transmit_chars()
423 zssync(uap); in pmz_transmit_chars()
426 uap->port.icount.tx++; in pmz_transmit_chars()
429 uart_write_wakeup(&uap->port); in pmz_transmit_chars()
434 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
435 zssync(uap); in pmz_transmit_chars()
441 struct uart_pmac_port *uap = dev_id; in pmz_interrupt() local
448 uap_a = pmz_get_port_A(uap); in pmz_interrupt()
477 tty_flip_buffer_push(&uap->port.state->port); in pmz_interrupt()
502 tty_flip_buffer_push(&uap->port.state->port); in pmz_interrupt()
511 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) in pmz_peek_status() argument
516 spin_lock_irqsave(&uap->port.lock, flags); in pmz_peek_status()
517 status = read_zsreg(uap, R0); in pmz_peek_status()
518 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_peek_status()
545 struct uart_pmac_port *uap = to_pmz(port); in pmz_set_mctrl() local
549 if (ZS_IS_IRDA(uap)) in pmz_set_mctrl()
552 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) in pmz_set_mctrl()
557 if (ZS_IS_INTMODEM(uap)) { in pmz_set_mctrl()
569 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
570 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
572 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
574 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
575 zssync(uap); in pmz_set_mctrl()
585 struct uart_pmac_port *uap = to_pmz(port); in pmz_get_mctrl() local
589 status = read_zsreg(uap, R0); in pmz_get_mctrl()
618 struct uart_pmac_port *uap = to_pmz(port); in pmz_start_tx() local
623 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; in pmz_start_tx()
624 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; in pmz_start_tx()
626 status = read_zsreg(uap, R0); in pmz_start_tx()
636 write_zsdata(uap, port->x_char); in pmz_start_tx()
637 zssync(uap); in pmz_start_tx()
645 write_zsdata(uap, xmit->buf[xmit->tail]); in pmz_start_tx()
646 zssync(uap); in pmz_start_tx()
651 uart_write_wakeup(&uap->port); in pmz_start_tx()
665 struct uart_pmac_port *uap = to_pmz(port); in pmz_stop_rx() local
670 uap->curregs[R1] &= ~RxINT_MASK; in pmz_stop_rx()
671 pmz_maybe_update_regs(uap); in pmz_stop_rx()
682 struct uart_pmac_port *uap = to_pmz(port); in pmz_enable_ms() local
685 if (ZS_IS_IRDA(uap)) in pmz_enable_ms()
687 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); in pmz_enable_ms()
688 if (new_reg != uap->curregs[R15]) { in pmz_enable_ms()
689 uap->curregs[R15] = new_reg; in pmz_enable_ms()
692 write_zsreg(uap, R15, uap->curregs[R15]); in pmz_enable_ms()
702 struct uart_pmac_port *uap = to_pmz(port); in pmz_break_ctl() local
715 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
716 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
717 uap->curregs[R5] = new_reg; in pmz_break_ctl()
718 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
732 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) in pmz_set_scc_power() argument
739 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); in pmz_set_scc_power()
741 if (ZS_IS_INTMODEM(uap)) { in pmz_set_scc_power()
743 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); in pmz_set_scc_power()
751 if (ZS_IS_INTMODEM(uap)) { in pmz_set_scc_power()
753 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); in pmz_set_scc_power()
756 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); in pmz_set_scc_power()
763 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) in pmz_set_scc_power() argument
790 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) in pmz_fix_zero_bug_scc() argument
792 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); in pmz_fix_zero_bug_scc()
793 zssync(uap); in pmz_fix_zero_bug_scc()
795 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); in pmz_fix_zero_bug_scc()
796 zssync(uap); in pmz_fix_zero_bug_scc()
798 write_zsreg(uap, 4, X1CLK | MONSYNC); in pmz_fix_zero_bug_scc()
799 write_zsreg(uap, 3, Rx8); in pmz_fix_zero_bug_scc()
800 write_zsreg(uap, 5, Tx8 | RTS); in pmz_fix_zero_bug_scc()
801 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ in pmz_fix_zero_bug_scc()
802 write_zsreg(uap, 11, RCBR | TCBR); in pmz_fix_zero_bug_scc()
803 write_zsreg(uap, 12, 0); in pmz_fix_zero_bug_scc()
804 write_zsreg(uap, 13, 0); in pmz_fix_zero_bug_scc()
805 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); in pmz_fix_zero_bug_scc()
806 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); in pmz_fix_zero_bug_scc()
807 write_zsreg(uap, 3, Rx8 | RxENABLE); in pmz_fix_zero_bug_scc()
808 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
809 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
810 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ in pmz_fix_zero_bug_scc()
817 write_zsreg(uap, 9, NV); in pmz_fix_zero_bug_scc()
818 write_zsreg(uap, 4, X16CLK | SB_MASK); in pmz_fix_zero_bug_scc()
819 write_zsreg(uap, 3, Rx8); in pmz_fix_zero_bug_scc()
821 while (read_zsreg(uap, 0) & Rx_CH_AV) { in pmz_fix_zero_bug_scc()
822 (void)read_zsreg(uap, 8); in pmz_fix_zero_bug_scc()
823 write_zsreg(uap, 0, RES_EXT_INT); in pmz_fix_zero_bug_scc()
824 write_zsreg(uap, 0, ERR_RES); in pmz_fix_zero_bug_scc()
834 static int __pmz_startup(struct uart_pmac_port *uap) in __pmz_startup() argument
838 memset(&uap->curregs, 0, sizeof(uap->curregs)); in __pmz_startup()
841 pwr_delay = pmz_set_scc_power(uap, 1); in __pmz_startup()
844 pmz_fix_zero_bug_scc(uap); in __pmz_startup()
847 uap->curregs[R9] = 0; in __pmz_startup()
848 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); in __pmz_startup()
849 zssync(uap); in __pmz_startup()
851 write_zsreg(uap, 9, 0); in __pmz_startup()
852 zssync(uap); in __pmz_startup()
855 write_zsreg(uap, R1, 0); in __pmz_startup()
856 write_zsreg(uap, R0, ERR_RES); in __pmz_startup()
857 write_zsreg(uap, R0, ERR_RES); in __pmz_startup()
858 write_zsreg(uap, R0, RES_H_IUS); in __pmz_startup()
859 write_zsreg(uap, R0, RES_H_IUS); in __pmz_startup()
862 uap->curregs[R4] = X16CLK | SB1; in __pmz_startup()
863 uap->curregs[R3] = Rx8; in __pmz_startup()
864 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
865 if (!ZS_IS_IRDA(uap)) in __pmz_startup()
866 uap->curregs[R5] |= DTR; in __pmz_startup()
867 uap->curregs[R12] = 0; in __pmz_startup()
868 uap->curregs[R13] = 0; in __pmz_startup()
869 uap->curregs[R14] = BRENAB; in __pmz_startup()
872 uap->curregs[R15] = BRKIE; in __pmz_startup()
875 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
877 pmz_load_zsregs(uap, uap->curregs); in __pmz_startup()
880 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); in __pmz_startup()
881 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
884 uap->prev_status = read_zsreg(uap, R0); in __pmz_startup()
889 static void pmz_irda_reset(struct uart_pmac_port *uap) in pmz_irda_reset() argument
893 spin_lock_irqsave(&uap->port.lock, flags); in pmz_irda_reset()
894 uap->curregs[R5] |= DTR; in pmz_irda_reset()
895 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
896 zssync(uap); in pmz_irda_reset()
897 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_irda_reset()
900 spin_lock_irqsave(&uap->port.lock, flags); in pmz_irda_reset()
901 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
902 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
903 zssync(uap); in pmz_irda_reset()
904 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_irda_reset()
914 struct uart_pmac_port *uap = to_pmz(port); in pmz_startup() local
920 uap->flags |= PMACZILOG_FLAG_IS_OPEN; in pmz_startup()
925 if (!ZS_IS_CONS(uap)) { in pmz_startup()
927 pwr_delay = __pmz_startup(uap); in pmz_startup()
930 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); in pmz_startup()
931 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, in pmz_startup()
932 uap->irq_name, uap)) { in pmz_startup()
934 pmz_set_scc_power(uap, 0); in pmz_startup()
947 if (ZS_IS_IRDA(uap)) in pmz_startup()
948 pmz_irda_reset(uap); in pmz_startup()
952 pmz_interrupt_control(uap, 1); in pmz_startup()
962 struct uart_pmac_port *uap = to_pmz(port); in pmz_shutdown() local
970 pmz_interrupt_control(uap, 0); in pmz_shutdown()
972 if (!ZS_IS_CONS(uap)) { in pmz_shutdown()
974 uap->curregs[R3] &= ~RxENABLE; in pmz_shutdown()
975 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
978 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
979 pmz_maybe_update_regs(uap); in pmz_shutdown()
985 free_irq(uap->port.irq, uap); in pmz_shutdown()
989 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; in pmz_shutdown()
991 if (!ZS_IS_CONS(uap)) in pmz_shutdown()
992 pmz_set_scc_power(uap, 0); /* Shut the chip down */ in pmz_shutdown()
1002 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, in pmz_convert_to_zs() argument
1011 if (baud >= 115200 && ZS_IS_IRDA(uap)) { in pmz_convert_to_zs()
1012 uap->curregs[R4] = X1CLK; in pmz_convert_to_zs()
1013 uap->curregs[R11] = RCTRxCP | TCTRxCP; in pmz_convert_to_zs()
1014 uap->curregs[R14] = 0; /* BRG off */ in pmz_convert_to_zs()
1015 uap->curregs[R12] = 0; in pmz_convert_to_zs()
1016 uap->curregs[R13] = 0; in pmz_convert_to_zs()
1017 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; in pmz_convert_to_zs()
1021 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
1022 uap->curregs[R11] = 0; in pmz_convert_to_zs()
1023 uap->curregs[R14] = 0; in pmz_convert_to_zs()
1026 uap->curregs[R4] = X32CLK; in pmz_convert_to_zs()
1027 uap->curregs[R11] = 0; in pmz_convert_to_zs()
1028 uap->curregs[R14] = 0; in pmz_convert_to_zs()
1031 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
1032 uap->curregs[R11] = TCBR | RCBR; in pmz_convert_to_zs()
1034 uap->curregs[R12] = (brg & 255); in pmz_convert_to_zs()
1035 uap->curregs[R13] = ((brg >> 8) & 255); in pmz_convert_to_zs()
1036 uap->curregs[R14] = BRENAB; in pmz_convert_to_zs()
1038 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; in pmz_convert_to_zs()
1042 uap->curregs[3] &= ~RxN_MASK; in pmz_convert_to_zs()
1043 uap->curregs[5] &= ~TxN_MASK; in pmz_convert_to_zs()
1047 uap->curregs[3] |= Rx5; in pmz_convert_to_zs()
1048 uap->curregs[5] |= Tx5; in pmz_convert_to_zs()
1049 uap->parity_mask = 0x1f; in pmz_convert_to_zs()
1052 uap->curregs[3] |= Rx6; in pmz_convert_to_zs()
1053 uap->curregs[5] |= Tx6; in pmz_convert_to_zs()
1054 uap->parity_mask = 0x3f; in pmz_convert_to_zs()
1057 uap->curregs[3] |= Rx7; in pmz_convert_to_zs()
1058 uap->curregs[5] |= Tx7; in pmz_convert_to_zs()
1059 uap->parity_mask = 0x7f; in pmz_convert_to_zs()
1063 uap->curregs[3] |= Rx8; in pmz_convert_to_zs()
1064 uap->curregs[5] |= Tx8; in pmz_convert_to_zs()
1065 uap->parity_mask = 0xff; in pmz_convert_to_zs()
1068 uap->curregs[4] &= ~(SB_MASK); in pmz_convert_to_zs()
1070 uap->curregs[4] |= SB2; in pmz_convert_to_zs()
1072 uap->curregs[4] |= SB1; in pmz_convert_to_zs()
1074 uap->curregs[4] |= PAR_ENAB; in pmz_convert_to_zs()
1076 uap->curregs[4] &= ~PAR_ENAB; in pmz_convert_to_zs()
1078 uap->curregs[4] |= PAR_EVEN; in pmz_convert_to_zs()
1080 uap->curregs[4] &= ~PAR_EVEN; in pmz_convert_to_zs()
1082 uap->port.read_status_mask = Rx_OVR; in pmz_convert_to_zs()
1084 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; in pmz_convert_to_zs()
1086 uap->port.read_status_mask |= BRK_ABRT; in pmz_convert_to_zs()
1088 uap->port.ignore_status_mask = 0; in pmz_convert_to_zs()
1090 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; in pmz_convert_to_zs()
1092 uap->port.ignore_status_mask |= BRK_ABRT; in pmz_convert_to_zs()
1094 uap->port.ignore_status_mask |= Rx_OVR; in pmz_convert_to_zs()
1098 uap->port.ignore_status_mask = 0xff; in pmz_convert_to_zs()
1105 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) in pmz_irda_setup() argument
1150 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 in pmz_irda_setup()
1151 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { in pmz_irda_setup()
1161 (void)read_zsdata(uap); in pmz_irda_setup()
1162 (void)read_zsdata(uap); in pmz_irda_setup()
1163 (void)read_zsdata(uap); in pmz_irda_setup()
1165 while (read_zsreg(uap, R0) & Rx_CH_AV) { in pmz_irda_setup()
1166 read_zsdata(uap); in pmz_irda_setup()
1175 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1176 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1177 zssync(uap); in pmz_irda_setup()
1181 pmz_convert_to_zs(uap, CS8, 0, 19200); in pmz_irda_setup()
1182 pmz_load_zsregs(uap, uap->curregs); in pmz_irda_setup()
1186 write_zsdata(uap, 1); in pmz_irda_setup()
1188 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { in pmz_irda_setup()
1195 version = read_zsdata(uap); in pmz_irda_setup()
1203 write_zsdata(uap, cmdbyte); in pmz_irda_setup()
1205 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { in pmz_irda_setup()
1212 t = read_zsdata(uap); in pmz_irda_setup()
1219 (void)read_zsdata(uap); in pmz_irda_setup()
1220 (void)read_zsdata(uap); in pmz_irda_setup()
1221 (void)read_zsdata(uap); in pmz_irda_setup()
1225 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1226 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1227 zssync(uap); in pmz_irda_setup()
1229 (void)read_zsdata(uap); in pmz_irda_setup()
1230 (void)read_zsdata(uap); in pmz_irda_setup()
1231 (void)read_zsdata(uap); in pmz_irda_setup()
1238 struct uart_pmac_port *uap = to_pmz(port); in __pmz_set_termios() local
1243 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); in __pmz_set_termios()
1252 if (ZS_IS_IRDA(uap)) { in __pmz_set_termios()
1257 pmz_irda_setup(uap, &baud); in __pmz_set_termios()
1259 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); in __pmz_set_termios()
1260 pmz_load_zsregs(uap, uap->curregs); in __pmz_set_termios()
1261 zssync(uap); in __pmz_set_termios()
1264 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); in __pmz_set_termios()
1266 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { in __pmz_set_termios()
1267 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; in __pmz_set_termios()
1268 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; in __pmz_set_termios()
1270 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); in __pmz_set_termios()
1271 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; in __pmz_set_termios()
1275 pmz_maybe_update_regs(uap); in __pmz_set_termios()
1286 struct uart_pmac_port *uap = to_pmz(port); in pmz_set_termios() local
1292 pmz_interrupt_control(uap, 0); in pmz_set_termios()
1298 if (ZS_IS_OPEN(uap)) in pmz_set_termios()
1299 pmz_interrupt_control(uap, 1); in pmz_set_termios()
1306 struct uart_pmac_port *uap = to_pmz(port); in pmz_type() local
1308 if (ZS_IS_IRDA(uap)) in pmz_type()
1310 else if (ZS_IS_INTMODEM(uap)) in pmz_type()
1342 struct uart_pmac_port *uap = in pmz_poll_get_char() local
1347 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) in pmz_poll_get_char()
1348 return read_zsdata(uap); in pmz_poll_get_char()
1358 struct uart_pmac_port *uap = in pmz_poll_put_char() local
1362 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) in pmz_poll_put_char()
1364 write_zsdata(uap, c); in pmz_poll_put_char()
1399 static int __init pmz_init_port(struct uart_pmac_port *uap) in pmz_init_port() argument
1401 struct device_node *np = uap->node; in pmz_init_port()
1415 uap->port.mapbase = r_ports.start; in pmz_init_port()
1416 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); in pmz_init_port()
1418 uap->control_reg = uap->port.membase; in pmz_init_port()
1419 uap->data_reg = uap->control_reg + 0x10; in pmz_init_port()
1427 uap->flags |= PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1432 if (ZS_HAS_DMA(uap)) { in pmz_init_port()
1433 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); in pmz_init_port()
1434 if (uap->tx_dma_regs == NULL) { in pmz_init_port()
1435 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1438 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); in pmz_init_port()
1439 if (uap->rx_dma_regs == NULL) { in pmz_init_port()
1440 iounmap(uap->tx_dma_regs); in pmz_init_port()
1441 uap->tx_dma_regs = NULL; in pmz_init_port()
1442 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; in pmz_init_port()
1445 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); in pmz_init_port()
1446 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); in pmz_init_port()
1454 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; in pmz_init_port()
1457 uap->flags |= PMACZILOG_FLAG_IS_IRDA; in pmz_init_port()
1458 uap->port_type = PMAC_SCC_ASYNC; in pmz_init_port()
1463 uap->flags |= PMACZILOG_FLAG_IS_IRDA; in pmz_init_port()
1465 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; in pmz_init_port()
1467 if (ZS_IS_IRDA(uap)) in pmz_init_port()
1468 uap->port_type = PMAC_SCC_IRDA; in pmz_init_port()
1469 if (ZS_IS_INTMODEM(uap)) { in pmz_init_port()
1482 uap->port_type = PMAC_SCC_I2S1; in pmz_init_port()
1495 uap->port.iotype = UPIO_MEM; in pmz_init_port()
1496 uap->port.irq = irq_of_parse_and_map(np, 0); in pmz_init_port()
1497 uap->port.uartclk = ZS_CLOCK; in pmz_init_port()
1498 uap->port.fifosize = 1; in pmz_init_port()
1499 uap->port.ops = &pmz_pops; in pmz_init_port()
1500 uap->port.type = PORT_PMAC_ZILOG; in pmz_init_port()
1501 uap->port.flags = 0; in pmz_init_port()
1509 if (uap->port.irq == 0 && in pmz_init_port()
1513 uap->port.irq = irq_create_mapping(NULL, 64 + 15); in pmz_init_port()
1514 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); in pmz_init_port()
1515 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); in pmz_init_port()
1522 pmz_convert_to_zs(uap, CS8, 0, 9600); in pmz_init_port()
1530 static void pmz_dispose_port(struct uart_pmac_port *uap) in pmz_dispose_port() argument
1534 np = uap->node; in pmz_dispose_port()
1535 iounmap(uap->rx_dma_regs); in pmz_dispose_port()
1536 iounmap(uap->tx_dma_regs); in pmz_dispose_port()
1537 iounmap(uap->control_reg); in pmz_dispose_port()
1538 uap->node = NULL; in pmz_dispose_port()
1540 memset(uap, 0, sizeof(struct uart_pmac_port)); in pmz_dispose_port()
1548 struct uart_pmac_port *uap; in pmz_attach() local
1560 uap = &pmz_ports[i]; in pmz_attach()
1561 uap->dev = mdev; in pmz_attach()
1562 uap->port.dev = &mdev->ofdev.dev; in pmz_attach()
1563 dev_set_drvdata(&mdev->ofdev.dev, uap); in pmz_attach()
1568 if (macio_request_resources(uap->dev, "pmac_zilog")) in pmz_attach()
1571 uap->node->name); in pmz_attach()
1573 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; in pmz_attach()
1575 return uart_add_one_port(&pmz_uart_reg, &uap->port); in pmz_attach()
1584 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_detach() local
1586 if (!uap) in pmz_detach()
1589 uart_remove_one_port(&pmz_uart_reg, &uap->port); in pmz_detach()
1591 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { in pmz_detach()
1592 macio_release_resources(uap->dev); in pmz_detach()
1593 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; in pmz_detach()
1596 uap->dev = NULL; in pmz_detach()
1597 uap->port.dev = NULL; in pmz_detach()
1605 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_suspend() local
1607 if (uap == NULL) { in pmz_suspend()
1612 uart_suspend_port(&pmz_uart_reg, &uap->port); in pmz_suspend()
1620 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); in pmz_resume() local
1622 if (uap == NULL) in pmz_resume()
1625 uart_resume_port(&pmz_uart_reg, &uap->port); in pmz_resume()
1703 static int __init pmz_init_port(struct uart_pmac_port *uap) in pmz_init_port() argument
1708 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); in pmz_init_port()
1709 irq = platform_get_irq(uap->pdev, 0); in pmz_init_port()
1713 uap->port.mapbase = r_ports->start; in pmz_init_port()
1714 uap->port.membase = (unsigned char __iomem *) r_ports->start; in pmz_init_port()
1715 uap->port.iotype = UPIO_MEM; in pmz_init_port()
1716 uap->port.irq = irq; in pmz_init_port()
1717 uap->port.uartclk = ZS_CLOCK; in pmz_init_port()
1718 uap->port.fifosize = 1; in pmz_init_port()
1719 uap->port.ops = &pmz_pops; in pmz_init_port()
1720 uap->port.type = PORT_PMAC_ZILOG; in pmz_init_port()
1721 uap->port.flags = 0; in pmz_init_port()
1723 uap->control_reg = uap->port.membase; in pmz_init_port()
1724 uap->data_reg = uap->control_reg + 4; in pmz_init_port()
1725 uap->port_type = 0; in pmz_init_port()
1727 pmz_convert_to_zs(uap, CS8, 0, 9600); in pmz_init_port()
1759 static void pmz_dispose_port(struct uart_pmac_port *uap) in pmz_dispose_port() argument
1761 memset(uap, 0, sizeof(struct uart_pmac_port)); in pmz_dispose_port()
1766 struct uart_pmac_port *uap; in pmz_attach() local
1776 uap = &pmz_ports[i]; in pmz_attach()
1777 uap->port.dev = &pdev->dev; in pmz_attach()
1778 platform_set_drvdata(pdev, uap); in pmz_attach()
1780 return uart_add_one_port(&pmz_uart_reg, &uap->port); in pmz_attach()
1785 struct uart_pmac_port *uap = platform_get_drvdata(pdev); in pmz_detach() local
1787 if (!uap) in pmz_detach()
1790 uart_remove_one_port(&pmz_uart_reg, &uap->port); in pmz_detach()
1792 uap->port.dev = NULL; in pmz_detach()
1945 struct uart_pmac_port *uap = in pmz_console_putchar() local
1949 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) in pmz_console_putchar()
1951 write_zsdata(uap, ch); in pmz_console_putchar()
1960 struct uart_pmac_port *uap = &pmz_ports[con->index]; in pmz_console_write() local
1963 spin_lock_irqsave(&uap->port.lock, flags); in pmz_console_write()
1966 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); in pmz_console_write()
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()
1969 uart_console_write(&uap->port, s, count, pmz_console_putchar); in pmz_console_write()
1972 write_zsreg(uap, R1, uap->curregs[1]); in pmz_console_write()
1975 spin_unlock_irqrestore(&uap->port.lock, flags); in pmz_console_write()
1983 struct uart_pmac_port *uap; in pmz_console_setup() local
2006 uap = &pmz_ports[co->index]; in pmz_console_setup()
2008 if (uap->node == NULL) in pmz_console_setup()
2011 if (uap->pdev == NULL) in pmz_console_setup()
2014 port = &uap->port; in pmz_console_setup()
2019 uap->flags |= PMACZILOG_FLAG_IS_CONS; in pmz_console_setup()
2029 pwr_delay = __pmz_startup(uap); in pmz_console_setup()