Lines Matching refs:R5
146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
178 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
569 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
570 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
572 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
574 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
715 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
716 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
717 uap->curregs[R5] = new_reg; in pmz_break_ctl()
718 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
864 uap->curregs[R5] = Tx8 | RTS; in __pmz_startup()
866 uap->curregs[R5] |= DTR; in __pmz_startup()
881 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); in __pmz_startup()
894 uap->curregs[R5] |= DTR; in pmz_irda_reset()
895 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
901 uap->curregs[R5] &= ~DTR; in pmz_irda_reset()
902 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_reset()
975 uap->curregs[R5] &= ~TxENABLE; in pmz_shutdown()
978 uap->curregs[R5] &= ~SND_BRK; in pmz_shutdown()
1175 uap->curregs[R5] |= DTR; in pmz_irda_setup()
1176 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1225 uap->curregs[R5] &= ~DTR; in pmz_irda_setup()
1226 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_irda_setup()
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); in pmz_console_write()