Lines Matching refs:UART_INTR
146 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) macro
184 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
187 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
201 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
203 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
214 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
216 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
389 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
391 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
434 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
660 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
663 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
673 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
674 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
749 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
767 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()