190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)  in msm_write()  function
206 	msm_write(port, 0x06, UART_MREG);  in msm_serial_set_mnd_regs_tcxo()
207 	msm_write(port, 0xF1, UART_NREG);  in msm_serial_set_mnd_regs_tcxo()
208 	msm_write(port, 0x0F, UART_DREG);  in msm_serial_set_mnd_regs_tcxo()
209 	msm_write(port, 0x1A, UART_MNDREG);  in msm_serial_set_mnd_regs_tcxo()
218 	msm_write(port, 0x18, UART_MREG);  in msm_serial_set_mnd_regs_tcxoby4()
219 	msm_write(port, 0xF6, UART_NREG);  in msm_serial_set_mnd_regs_tcxoby4()
220 	msm_write(port, 0x0F, UART_DREG);  in msm_serial_set_mnd_regs_tcxoby4()
221 	msm_write(port, 0x0A, UART_MNDREG);  in msm_serial_set_mnd_regs_tcxoby4()
265 	msm_write(port, val, UARTDM_DMEN);  in msm_stop_dma()
391 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
399 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_tx()
412 	msm_write(port, msm_port->imr, UART_IMR);  in msm_start_tx()
418 	msm_write(port, count, UARTDM_NCF_TX);  in msm_reset_dm_count()
446 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_tx_dma()
449 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
450 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
462 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_tx_dma()
510 	msm_write(port, msm_port->imr, UART_IMR);  in msm_handle_tx_dma()
518 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
523 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
550 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_rx_dma()
555 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
637 	msm_write(uart, msm_port->imr, UART_IMR);  in msm_start_rx_dma()
643 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
644 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
650 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
652 	msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);  in msm_start_rx_dma()
655 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
668 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_rx()
679 	msm_write(port, msm_port->imr, UART_IMR);  in msm_enable_ms()
692 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
749 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
750 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_handle_rx_dm()
751 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
769 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
912 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
928 	msm_write(port, 0, UART_IMR); /* disable interrupt */  in msm_uart_irq()
932 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
938 			msm_write(port, val, UART_CR);  in msm_uart_irq()
940 			msm_write(port, val, UART_CR);  in msm_uart_irq()
957 	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */  in msm_uart_irq()
978 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
979 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
980 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
981 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
982 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
983 	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);  in msm_reset()
987 		msm_write(port, 0, UARTDM_DMEN);  in msm_reset()
998 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
999 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
1002 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
1009 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
1011 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
1108 	msm_write(port, entry->code, UART_CSR);  in msm_set_baud_rate()
1122 	msm_write(port, watermark, UART_IPR);  in msm_set_baud_rate()
1126 	msm_write(port, watermark, UART_RFWR);  in msm_set_baud_rate()
1129 	msm_write(port, 10, UART_TFWR);  in msm_set_baud_rate()
1131 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
1135 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
1141 	msm_write(port, msm_port->imr, UART_IMR);  in msm_set_baud_rate()
1144 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
1145 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_set_baud_rate()
1146 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
1189 	msm_write(port, data, UART_MR1);  in msm_startup()
1218 	msm_write(port, 0, UART_IMR); /* disable interrupts */  in msm_shutdown()
1285 	msm_write(port, mr, UART_MR2);  in msm_set_termios()
1294 	msm_write(port, mr, UART_MR1);  in msm_set_termios()
1433 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1437 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1438 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_poll_get_char_dm()
1439 			msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,  in msm_poll_get_char_dm()
1462 	msm_write(port, 0, UART_IMR);  in msm_poll_get_char()
1470 	msm_write(port, imr, UART_IMR);  in msm_poll_get_char()
1482 	msm_write(port, 0, UART_IMR);  in msm_poll_put_char()
1492 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);  in msm_poll_put_char()
1499 	msm_write(port, imr, UART_IMR);  in msm_poll_put_char()