409 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))  macro
429 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
430 	out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
431 	out_be32(&FIFO_512x(port)->txalarm, 1);  in mpc512x_psc_fifo_init()
432 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_fifo_init()
434 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);  in mpc512x_psc_fifo_init()
435 	out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);  in mpc512x_psc_fifo_init()
436 	out_be32(&FIFO_512x(port)->rxalarm, 1);  in mpc512x_psc_fifo_init()
437 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_fifo_init()
439 	out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
440 	out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);  in mpc512x_psc_fifo_init()
445 	return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);  in mpc512x_psc_raw_rx_rdy()
450 	return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);  in mpc512x_psc_raw_tx_rdy()
455 	return in_be32(&FIFO_512x(port)->rxsr)  in mpc512x_psc_rx_rdy()
456 	    & in_be32(&FIFO_512x(port)->rximr)  in mpc512x_psc_rx_rdy()
462 	return in_be32(&FIFO_512x(port)->txsr)  in mpc512x_psc_tx_rdy()
463 	    & in_be32(&FIFO_512x(port)->tximr)  in mpc512x_psc_tx_rdy()
469 	return in_be32(&FIFO_512x(port)->txsr)  in mpc512x_psc_tx_empty()
477 	rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);  in mpc512x_psc_stop_rx()
479 	out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);  in mpc512x_psc_stop_rx()
486 	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);  in mpc512x_psc_start_tx()
488 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_start_tx()
495 	tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);  in mpc512x_psc_stop_tx()
497 	out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);  in mpc512x_psc_stop_tx()
502 	out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));  in mpc512x_psc_rx_clr_irq()
507 	out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));  in mpc512x_psc_tx_clr_irq()
512 	out_8(&FIFO_512x(port)->txdata_8, c);  in mpc512x_psc_write_char()
517 	return in_8(&FIFO_512x(port)->rxdata_8);  in mpc512x_psc_read_char()
523 		in_be32(&FIFO_512x(port)->tximr) << 16 |  in mpc512x_psc_cw_disable_ints()
524 		in_be32(&FIFO_512x(port)->rximr);  in mpc512x_psc_cw_disable_ints()
525 	out_be32(&FIFO_512x(port)->tximr, 0);  in mpc512x_psc_cw_disable_ints()
526 	out_be32(&FIFO_512x(port)->rximr, 0);  in mpc512x_psc_cw_disable_ints()
531 	out_be32(&FIFO_512x(port)->tximr,  in mpc512x_psc_cw_restore_ints()
533 	out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);  in mpc512x_psc_cw_restore_ints()