Lines Matching refs:max310x_port_write
294 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) in max310x_port_write() function
514 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); in max310x_set_baud()
515 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); in max310x_set_baud()
516 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); in max310x_set_baud()
726 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
914 max310x_port_write(port, MAX310X_LCR_REG, lcr); in max310x_set_termios()
935 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
936 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
946 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); in max310x_set_termios()
967 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val); in max310x_rs_proc()
1015 max310x_port_write(port, MAX310X_MODE2_REG, val); in max310x_startup()
1021 max310x_port_write(port, MAX310X_FLOWLVL_REG, in max310x_startup()
1029 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); in max310x_startup()
1039 max310x_port_write(port, MAX310X_IRQEN_REG, 0); in max310x_shutdown()
1297 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()