Lines Matching refs:writeb
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
73 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
81 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
86 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | in cls_set_cts_flow_control()
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
115 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
117 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
120 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
128 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
133 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | in cls_set_ixon_flow_control()
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
159 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
167 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
172 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | in cls_set_no_output_flow_control()
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
202 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
206 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
211 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | in cls_set_rts_flow_control()
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
241 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
243 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
246 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
250 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
255 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | in cls_set_ixoff_flow_control()
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
281 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
285 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
290 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | in cls_set_no_input_flow_control()
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
330 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
338 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
484 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
615 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), in cls_flush_uart_write()
659 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
670 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
764 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
765 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
766 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
767 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
771 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
778 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
864 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
870 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
877 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
880 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
885 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), in cls_uart_init()
901 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
938 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
952 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()