Lines Matching refs:sOutW
1855 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sPCIInitController()
2597 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sInitController()
2654 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ in sReadAiopNumChan()
2656 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ in sReadAiopNumChan()
2785 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sInitChan()
2786 sOutW(ChP->IndexData, 0); in sInitChan()
2792 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sInitChan()
2793 sOutW(ChP->IndexData, 0); in sInitChan()
2794 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sInitChan()
2795 sOutW(ChP->IndexData, 0); in sInitChan()
2797 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); in sInitChan()
2800 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); in sInitChan()
2871 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sFlushRxFIFO()
2872 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2873 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sFlushRxFIFO()
2874 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2913 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sFlushTxFIFO()
2914 sOutW(ChP->IndexData, 0); in sFlushTxFIFO()
2941 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ in sWriteTxPrioByte()