267 	u32 config_reg;  in zynqmp_qspi_init_hw()  local
289 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_init_hw()
290 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_init_hw()
292 	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;  in zynqmp_qspi_init_hw()
294 	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;  in zynqmp_qspi_init_hw()
296 	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;  in zynqmp_qspi_init_hw()
298 	config_reg |= GQSPI_CFG_WP_HOLD_MASK;  in zynqmp_qspi_init_hw()
300 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_init_hw()
302 	config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_init_hw()
304 	config_reg &= ~GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_init_hw()
305 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_init_hw()
458 	u32 config_reg, req_hz, baud_rate_val = 0;  in zynqmp_qspi_setup_transfer()  local
474 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_setup_transfer()
477 	config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);  in zynqmp_qspi_setup_transfer()
480 		config_reg |= GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_setup_transfer()
482 		config_reg |= GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_setup_transfer()
484 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_setup_transfer()
485 	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);  in zynqmp_qspi_setup_transfer()
486 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_setup_transfer()
569 	u32 config_reg, genfifoentry;  in zynqmp_process_dma_irq()  local
583 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_process_dma_irq()
584 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_process_dma_irq()
585 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_process_dma_irq()
696 	u32 rx_bytes, rx_rem, config_reg;  in zynq_qspi_setuprxdma()  local
703 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynq_qspi_setuprxdma()
704 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynq_qspi_setuprxdma()
705 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynq_qspi_setuprxdma()
728 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynq_qspi_setuprxdma()
729 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynq_qspi_setuprxdma()
730 	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;  in zynq_qspi_setuprxdma()
731 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynq_qspi_setuprxdma()
753 	u32 config_reg;  in zynqmp_qspi_txrxsetup()  local
765 			config_reg = zynqmp_gqspi_read(xqspi,  in zynqmp_qspi_txrxsetup()
767 			config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_txrxsetup()
769 								config_reg);  in zynqmp_qspi_txrxsetup()