Lines Matching refs:SPI_SH_CR1
34 #define SPI_SH_CR1 0x08 macro
141 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_wait_receive_buffer()
153 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) { in spi_sh_wait_write_buffer_empty()
171 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
179 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF); in spi_sh_send()
209 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_send()
210 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
240 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_receive()
241 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_receive()
254 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_receive()
324 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1); in spi_sh_work()
328 SPI_SH_CR1); in spi_sh_work()
342 SPI_SH_CR1); in spi_sh_work()
353 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ in spi_sh_setup()
354 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */ in spi_sh_setup()
379 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_transfer()
396 SPI_SH_CR1); in spi_sh_cleanup()
404 cr1 = spi_sh_read(ss, SPI_SH_CR1); in spi_sh_irq()