192 	writel_relaxed(val, base + SE_IRQ_EN);  in geni_se_io_set_mode()
196 	writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);  in geni_se_io_set_mode()
198 	writel_relaxed(0, base + SE_GSI_EVENT_EN);  in geni_se_io_set_mode()
207 	writel_relaxed(val, base + GENI_CGC_CTRL);  in geni_se_io_init()
212 	writel_relaxed(val, base + SE_DMA_GENERAL_CFG);  in geni_se_io_init()
214 	writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);  in geni_se_io_init()
215 	writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);  in geni_se_io_init()
234 	writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);  in geni_se_init()
235 	writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);  in geni_se_init()
239 	writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_init()
243 	writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_init()
252 	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);  in geni_se_select_fifo_mode()
253 	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_se_select_fifo_mode()
254 	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);  in geni_se_select_fifo_mode()
255 	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);  in geni_se_select_fifo_mode()
256 	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);  in geni_se_select_fifo_mode()
257 	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);  in geni_se_select_fifo_mode()
264 	writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_fifo_mode()
269 	writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_select_fifo_mode()
273 	writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_fifo_mode()
280 	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);  in geni_se_select_dma_mode()
281 	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_se_select_dma_mode()
282 	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);  in geni_se_select_dma_mode()
283 	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);  in geni_se_select_dma_mode()
284 	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);  in geni_se_select_dma_mode()
285 	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);  in geni_se_select_dma_mode()
289 	writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_dma_mode()
412 		writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);  in geni_se_config_packing()
413 		writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);  in geni_se_config_packing()
416 		writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);  in geni_se_config_packing()
417 		writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);  in geni_se_config_packing()
428 		writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);  in geni_se_config_packing()
625 	writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);  in geni_se_tx_dma_prep()
626 	writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);  in geni_se_tx_dma_prep()
627 	writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);  in geni_se_tx_dma_prep()
628 	writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);  in geni_se_tx_dma_prep()
629 	writel_relaxed(len, se->base + SE_DMA_TX_LEN);  in geni_se_tx_dma_prep()
658 	writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);  in geni_se_rx_dma_prep()
659 	writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);  in geni_se_rx_dma_prep()
660 	writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);  in geni_se_rx_dma_prep()
662 	writel_relaxed(0, se->base + SE_DMA_RX_ATTR);  in geni_se_rx_dma_prep()
663 	writel_relaxed(len, se->base + SE_DMA_RX_LEN);  in geni_se_rx_dma_prep()