94 	unsigned int *reg_num, unsigned int *shift)  in get_cmxucr_reg()  argument
100 	*shift = 16 - 8 * (ucc_num & 2);  in get_cmxucr_reg()
107 	unsigned int shift;  in ucc_mux_set_grant_tsa_bkpt()  local
113 	get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);  in ucc_mux_set_grant_tsa_bkpt()
116 		setbits32(cmxucr, mask << shift);  in ucc_mux_set_grant_tsa_bkpt()
118 		clrbits32(cmxucr, mask << shift);  in ucc_mux_set_grant_tsa_bkpt()
128 	unsigned int shift;  in ucc_set_qe_mux_rxtx()  local
139 	get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);  in ucc_set_qe_mux_rxtx()
212 		shift += 4;  in ucc_set_qe_mux_rxtx()
214 	clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,  in ucc_set_qe_mux_rxtx()
215 		clock_bits << shift);  in ucc_set_qe_mux_rxtx()
510 	u32 shift;  in ucc_get_tdm_clk_shift()  local
512 	shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;  in ucc_get_tdm_clk_shift()
514 		shift -= tdm_num * 4;  in ucc_get_tdm_clk_shift()
516 		shift -= (tdm_num - 4) * 4;  in ucc_get_tdm_clk_shift()
518 	return shift;  in ucc_get_tdm_clk_shift()
525 	u32 shift;  in ucc_set_tdm_rxtx_clk()  local
542 	shift = ucc_get_tdm_clk_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_clk()
547 	qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,  in ucc_set_tdm_rxtx_clk()
548 			clock_bits << shift);  in ucc_set_tdm_rxtx_clk()
627 	u32 shift;  in ucc_get_tdm_sync_shift()  local
629 	shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;  in ucc_get_tdm_sync_shift()
630 	shift -= tdm_num * 2;  in ucc_get_tdm_sync_shift()
632 	return shift;  in ucc_get_tdm_sync_shift()
639 	u32 shift;  in ucc_set_tdm_rxtx_sync()  local
655 	shift = ucc_get_tdm_sync_shift(mode, tdm_num);  in ucc_set_tdm_rxtx_sync()
658 			QE_CMXUCR_TX_CLK_SRC_MASK << shift,  in ucc_set_tdm_rxtx_sync()
659 			source << shift);  in ucc_set_tdm_rxtx_sync()