37 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
39 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
41 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,  in tc_dwc_g210_setup_40bit_rmmi()
43 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_40bit_rmmi()
45 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
47 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
49 		{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,  in tc_dwc_g210_setup_40bit_rmmi()
51 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
55 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
57 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_40bit_rmmi()
59 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_40bit_rmmi()
61 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_40bit_rmmi()
63 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_40bit_rmmi()
65 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
67 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
69 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_40bit_rmmi()
71 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_40bit_rmmi()
73 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
75 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
94 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
96 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
98 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
100 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
102 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
104 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
106 		{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
108 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
112 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
114 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
116 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
118 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
120 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
122 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
124 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
126 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
128 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
151 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
153 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
155 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
157 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
162 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
164 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
166 		{ UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
168 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
170 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
172 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
174 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
176 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
178 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
180 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
182 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
184 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
186 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane1()