275 		reg_val = readw(&ha->reg->ctrl_status);  in qla4xxx_isp_check_reg()
4642 	uint32_t ctrl_status;  in qla4xxx_hw_reset()  local
4656 	ctrl_status = readw(&ha->reg->ctrl_status);  in qla4xxx_hw_reset()
4657 	if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0)  in qla4xxx_hw_reset()
4658 		writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);  in qla4xxx_hw_reset()
4661 	writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);  in qla4xxx_hw_reset()
4662 	readl(&ha->reg->ctrl_status);  in qla4xxx_hw_reset()
4677 	uint32_t ctrl_status;  in qla4xxx_soft_reset()  local
4688 		ctrl_status = readw(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4691 		if ((ctrl_status & CSR_NET_RESET_INTR) == 0)  in qla4xxx_soft_reset()
4697 	if ((ctrl_status & CSR_NET_RESET_INTR) != 0) {  in qla4xxx_soft_reset()
4703 		writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4704 		readl(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4712 		ctrl_status = readw(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4715 		if ((ctrl_status & CSR_SOFT_RESET) == 0) {  in qla4xxx_soft_reset()
4728 	ctrl_status = readw(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4729 	if ((ctrl_status & CSR_SCSI_RESET_INTR) != 0) {  in qla4xxx_soft_reset()
4730 		writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4731 		readl(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4744 		writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4745 		readl(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4751 			ctrl_status = readw(&ha->reg->ctrl_status);  in qla4xxx_soft_reset()
4754 			if ((ctrl_status & CSR_FORCE_SOFT_RESET) == 0) {  in qla4xxx_soft_reset()
5381 			while ((readw(&ha->reg->ctrl_status) &  in qla4xxx_do_dpc()
5458 		       &ha->reg->ctrl_status);  in qla4xxx_free_adapter()
5459 		readl(&ha->reg->ctrl_status);  in qla4xxx_free_adapter()