Lines Matching refs:hccr
2321 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); in qla2300_pci_config()
2323 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()
2344 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); in qla2300_pci_config()
2346 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()
2508 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); in qla2x00_reset_chip()
2511 if ((RD_REG_WORD(®->hccr) & in qla2x00_reset_chip()
2517 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2559 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
2560 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2563 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
2564 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2567 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); in qla2x00_reset_chip()
2568 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); in qla2x00_reset_chip()
2591 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
2596 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
2597 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2615 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); in qla2x00_reset_chip()
2616 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2672 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()
2698 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()
2716 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()
2736 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); in qla24xx_reset_risc()
2737 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()
2739 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); in qla24xx_reset_risc()
2740 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()
2742 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); in qla24xx_reset_risc()
2743 RD_REG_DWORD(®->hccr); in qla24xx_reset_risc()
2759 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()
2806 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); in qla25xx_manipulate_risc_semaphore()
2926 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); in qla2x00_chip_diag()
2927 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); in qla2x00_chip_diag()
3500 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); in qla2x00_setup_chip()
3501 RD_REG_WORD(®->hccr); in qla2x00_setup_chip()
3589 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); in qla2x00_setup_chip()
3592 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); in qla2x00_setup_chip()
3593 RD_REG_WORD(®->hccr); in qla2x00_setup_chip()
3912 RD_REG_DWORD(&ioreg->hccr); in qla24xx_config_rings()
6849 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); in qla2x00_reset_adapter()
6850 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_adapter()
6851 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_adapter()
6852 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_adapter()
6870 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); in qla24xx_reset_adapter()
6871 RD_REG_DWORD(®->hccr); in qla24xx_reset_adapter()
6872 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); in qla24xx_reset_adapter()
6873 RD_REG_DWORD(®->hccr); in qla24xx_reset_adapter()