Lines Matching refs:BIT_5
70 #define BIT_5 0x20 macro
315 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
692 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
998 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1019 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1171 #define MBX_5 BIT_5
1741 #define CF_READ BIT_5
1836 #define PO_DISABLE_INCR_REF_TAG BIT_5
1925 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2360 #define NVME_PRLI_SP_INITIATOR BIT_5
2470 #define FCF_ASYNC_ACTIVE BIT_5
3725 #define DT_ISP6312 BIT_5
4279 #define DFLG_DEV_FAILED BIT_5
4569 #define FC_LL_I BIT_5 /* Intermidiate*/
4579 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4587 #define FC_MED_MI BIT_5 /* Min Coax */
4596 #define FC_SP_16 BIT_5