Lines Matching refs:mvi
82 ((void *) mvi->rx_fis + 0x100 * id)
84 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
110 int (*chip_init)(struct mvs_info *mvi);
111 int (*spi_init)(struct mvs_info *mvi);
112 int (*chip_ioremap)(struct mvs_info *mvi);
113 void (*chip_iounmap)(struct mvs_info *mvi);
114 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
115 u32 (*isr_status)(struct mvs_info *mvi, int irq);
116 void (*interrupt_enable)(struct mvs_info *mvi);
117 void (*interrupt_disable)(struct mvs_info *mvi);
119 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
120 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
122 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
123 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
124 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
126 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
127 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
128 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
130 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
131 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
133 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
134 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
136 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
137 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
138 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
140 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
141 u32 (*rx_update)(struct mvs_info *mvi);
142 void (*int_full)(struct mvs_info *mvi);
143 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
144 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
148 void (*detect_porttype)(struct mvs_info *mvi, int i);
149 int (*oob_done)(struct mvs_info *mvi, int i);
150 void (*fix_phy_info)(struct mvs_info *mvi, int i,
152 void (*phy_work_around)(struct mvs_info *mvi, int i);
153 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
156 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
157 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
158 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
159 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
160 void (*clear_active_cmds)(struct mvs_info *mvi);
161 u32 (*spi_read_data)(struct mvs_info *mvi);
162 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
163 int (*spi_buildcmd)(struct mvs_info *mvi,
170 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
171 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
172 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
174 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
175 void (*non_spec_ncq_error)(struct mvs_info *mvi);
191 #define MVS_MAX_SG (1U << mvi->chip->sg_width)
192 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
194 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
195 #define MVS_CHIP_DISP (mvi->chip->dispatch)
222 struct mvs_info *mvi; member
424 struct mvs_info *mvi[2]; member
430 struct mvs_info *mvi; member
446 void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
447 void mvs_tag_free(struct mvs_info *mvi, u32 tag);
448 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
449 int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
450 void mvs_tag_init(struct mvs_info *mvi);
452 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
453 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
456 void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
470 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
473 void mvs_release_task(struct mvs_info *mvi,
475 void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
477 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
478 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
479 int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
480 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);