30 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)  in mvs_64xx_detect_porttype()  argument
32 	void __iomem *regs = mvi->regs;  in mvs_64xx_detect_porttype()
34 	struct mvs_phy *phy = &mvi->phy[i];  in mvs_64xx_detect_porttype()
44 static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)  in mvs_64xx_enable_xmt()  argument
46 	void __iomem *regs = mvi->regs;  in mvs_64xx_enable_xmt()
50 	if (mvi->chip->n_phy <= MVS_SOC_PORTS)  in mvs_64xx_enable_xmt()
57 static void mvs_64xx_phy_hacks(struct mvs_info *mvi)  in mvs_64xx_phy_hacks()  argument
59 	void __iomem *regs = mvi->regs;  in mvs_64xx_phy_hacks()
62 	mvs_phy_hacks(mvi);  in mvs_64xx_phy_hacks()
64 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_phy_hacks()
66 			mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8);  in mvs_64xx_phy_hacks()
67 			mvs_write_port_vsr_data(mvi, i, 0x2F0);  in mvs_64xx_phy_hacks()
72 		for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_phy_hacks()
73 			mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);  in mvs_64xx_phy_hacks()
74 			mvs_write_port_vsr_data(mvi, i, 0x90000000);  in mvs_64xx_phy_hacks()
75 			mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);  in mvs_64xx_phy_hacks()
76 			mvs_write_port_vsr_data(mvi, i, 0x50f2);  in mvs_64xx_phy_hacks()
77 			mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);  in mvs_64xx_phy_hacks()
78 			mvs_write_port_vsr_data(mvi, i, 0x0e);  in mvs_64xx_phy_hacks()
83 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)  in mvs_64xx_stp_reset()  argument
85 	void __iomem *regs = mvi->regs;  in mvs_64xx_stp_reset()
88 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_stp_reset()
90 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &reg);  in mvs_64xx_stp_reset()
92 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &reg);  in mvs_64xx_stp_reset()
103 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_stp_reset()
105 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);  in mvs_64xx_stp_reset()
107 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);  in mvs_64xx_stp_reset()
109 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);  in mvs_64xx_stp_reset()
111 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);  in mvs_64xx_stp_reset()
120 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)  in mvs_64xx_phy_reset()  argument
123 	tmp = mvs_read_port_irq_stat(mvi, phy_id);  in mvs_64xx_phy_reset()
125 	mvs_write_port_irq_stat(mvi, phy_id, tmp);  in mvs_64xx_phy_reset()
126 	tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_64xx_phy_reset()
131 	mvs_write_phy_ctl(mvi, phy_id, tmp);  in mvs_64xx_phy_reset()
134 			tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_64xx_phy_reset()
140 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)  in mvs_64xx_clear_srs_irq()  argument
142 	void __iomem *regs = mvi->regs;  in mvs_64xx_clear_srs_irq()
160 static int mvs_64xx_chip_reset(struct mvs_info *mvi)  in mvs_64xx_chip_reset()  argument
162 	void __iomem *regs = mvi->regs;  in mvs_64xx_chip_reset()
172 		if (mvi->flags & MVF_PHY_PWR_FIX) {  in mvs_64xx_chip_reset()
173 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);  in mvs_64xx_chip_reset()
176 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);  in mvs_64xx_chip_reset()
178 			pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);  in mvs_64xx_chip_reset()
181 			pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);  in mvs_64xx_chip_reset()
204 		dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");  in mvs_64xx_chip_reset()
210 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)  in mvs_64xx_phy_disable()  argument
212 	void __iomem *regs = mvi->regs;  in mvs_64xx_phy_disable()
214 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_phy_disable()
222 		pci_read_config_dword(mvi->pdev, offs, &tmp);  in mvs_64xx_phy_disable()
224 		pci_write_config_dword(mvi->pdev, offs, tmp);  in mvs_64xx_phy_disable()
232 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)  in mvs_64xx_phy_enable()  argument
234 	void __iomem *regs = mvi->regs;  in mvs_64xx_phy_enable()
236 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_phy_enable()
244 		pci_read_config_dword(mvi->pdev, offs, &tmp);  in mvs_64xx_phy_enable()
246 		pci_write_config_dword(mvi->pdev, offs, tmp);  in mvs_64xx_phy_enable()
254 static int mvs_64xx_init(struct mvs_info *mvi)  in mvs_64xx_init()  argument
256 	void __iomem *regs = mvi->regs;  in mvs_64xx_init()
260 	if (mvi->pdev && mvi->pdev->revision == 0)  in mvs_64xx_init()
261 		mvi->flags |= MVF_PHY_PWR_FIX;  in mvs_64xx_init()
262 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_init()
263 		mvs_show_pcie_usage(mvi);  in mvs_64xx_init()
264 		tmp = mvs_64xx_chip_reset(mvi);  in mvs_64xx_init()
282 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_init()
284 		pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);  in mvs_64xx_init()
287 		pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);  in mvs_64xx_init()
289 		pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);  in mvs_64xx_init()
292 		pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);  in mvs_64xx_init()
294 		pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);  in mvs_64xx_init()
297 		pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);  in mvs_64xx_init()
314 	mvs_64xx_phy_hacks(mvi);  in mvs_64xx_init()
316 	tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);  in mvs_64xx_init()
319 	mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);  in mvs_64xx_init()
324 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);  in mvs_64xx_init()
325 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);  in mvs_64xx_init()
327 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);  in mvs_64xx_init()
328 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);  in mvs_64xx_init()
331 	mw32(MVS_TX_LO, mvi->tx_dma);  in mvs_64xx_init()
332 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);  in mvs_64xx_init()
335 	mw32(MVS_RX_LO, mvi->rx_dma);  in mvs_64xx_init()
336 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);  in mvs_64xx_init()
338 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_init()
341 		mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,  in mvs_64xx_init()
342 				cpu_to_be64(mvi->phy[i].dev_sas_addr));  in mvs_64xx_init()
344 		mvs_64xx_enable_xmt(mvi, i);  in mvs_64xx_init()
346 		mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);  in mvs_64xx_init()
348 		mvs_64xx_detect_porttype(mvi, i);  in mvs_64xx_init()
350 	if (mvi->flags & MVF_FLAG_SOC) {  in mvs_64xx_init()
361 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_init()
363 		tmp = mvs_read_port_irq_stat(mvi, i);  in mvs_64xx_init()
365 		mvs_write_port_irq_stat(mvi, i, tmp);  in mvs_64xx_init()
371 		mvs_write_port_irq_mask(mvi, i, tmp);  in mvs_64xx_init()
374 		mvs_update_phyinfo(mvi, i, 1);  in mvs_64xx_init()
423 static int mvs_64xx_ioremap(struct mvs_info *mvi)  in mvs_64xx_ioremap()  argument
425 	if (!mvs_ioremap(mvi, 4, 2))  in mvs_64xx_ioremap()
430 static void mvs_64xx_iounmap(struct mvs_info *mvi)  in mvs_64xx_iounmap()  argument
432 	mvs_iounmap(mvi->regs);  in mvs_64xx_iounmap()
433 	mvs_iounmap(mvi->regs_ex);  in mvs_64xx_iounmap()
436 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)  in mvs_64xx_interrupt_enable()  argument
438 	void __iomem *regs = mvi->regs;  in mvs_64xx_interrupt_enable()
445 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)  in mvs_64xx_interrupt_disable()  argument
447 	void __iomem *regs = mvi->regs;  in mvs_64xx_interrupt_disable()
454 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)  in mvs_64xx_isr_status()  argument
456 	void __iomem *regs = mvi->regs;  in mvs_64xx_isr_status()
459 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_64xx_isr_status()
469 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)  in mvs_64xx_isr()  argument
471 	void __iomem *regs = mvi->regs;  in mvs_64xx_isr()
476 	spin_lock(&mvi->lock);  in mvs_64xx_isr()
477 	mvs_int_full(mvi);  in mvs_64xx_isr()
478 	spin_unlock(&mvi->lock);  in mvs_64xx_isr()
483 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)  in mvs_64xx_command_active()  argument
486 	mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));  in mvs_64xx_command_active()
487 	mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));  in mvs_64xx_command_active()
489 		tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));  in mvs_64xx_command_active()
492 		tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));  in mvs_64xx_command_active()
496 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,  in mvs_64xx_issue_stop()  argument
499 	void __iomem *regs = mvi->regs;  in mvs_64xx_issue_stop()
511 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)  in mvs_64xx_free_reg_set()  argument
513 	void __iomem *regs = mvi->regs;  in mvs_64xx_free_reg_set()
536 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)  in mvs_64xx_assign_reg_set()  argument
540 	void __iomem *regs = mvi->regs;  in mvs_64xx_assign_reg_set()
547 	for (i = 0; i < mvi->chip->srs_sz; i++) {  in mvs_64xx_assign_reg_set()
579 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)  in mvs_64xx_oob_done()  argument
582 	mvs_write_port_cfg_addr(mvi, i,  in mvs_64xx_oob_done()
584 	phy_st = mvs_read_port_cfg_data(mvi, i);  in mvs_64xx_oob_done()
590 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,  in mvs_64xx_fix_phy_info()  argument
594 	struct mvs_phy *phy = &mvi->phy[i];  in mvs_64xx_fix_phy_info()
608 	mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);  in mvs_64xx_fix_phy_info()
609 	phy->dev_info = mvs_read_port_cfg_data(mvi, i);  in mvs_64xx_fix_phy_info()
611 	mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);  in mvs_64xx_fix_phy_info()
612 	phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);  in mvs_64xx_fix_phy_info()
614 	mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);  in mvs_64xx_fix_phy_info()
616 	     (u64) mvs_read_port_cfg_data(mvi, i) << 32;  in mvs_64xx_fix_phy_info()
617 	mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);  in mvs_64xx_fix_phy_info()
618 	phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);  in mvs_64xx_fix_phy_info()
622 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)  in mvs_64xx_phy_work_around()  argument
625 	struct mvs_phy *phy = &mvi->phy[i];  in mvs_64xx_phy_work_around()
626 	mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);  in mvs_64xx_phy_work_around()
627 	tmp = mvs_read_port_vsr_data(mvi, i);  in mvs_64xx_phy_work_around()
634 	mvs_write_port_vsr_data(mvi, i, tmp);  in mvs_64xx_phy_work_around()
637 static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,  in mvs_64xx_phy_set_link_rate()  argument
643 	tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_64xx_phy_set_link_rate()
655 	mvs_write_phy_ctl(mvi, phy_id, tmp);  in mvs_64xx_phy_set_link_rate()
656 	mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);  in mvs_64xx_phy_set_link_rate()
659 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)  in mvs_64xx_clear_active_cmds()  argument
662 	void __iomem *regs = mvi->regs;  in mvs_64xx_clear_active_cmds()
672 static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)  in mvs_64xx_spi_read_data()  argument
674 	void __iomem *regs = mvi->regs_ex;  in mvs_64xx_spi_read_data()
678 static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)  in mvs_64xx_spi_write_data()  argument
680 	void __iomem *regs = mvi->regs_ex;  in mvs_64xx_spi_write_data()
685 static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,  in mvs_64xx_spi_buildcmd()  argument
709 static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)  in mvs_64xx_spi_issuecmd()  argument
711 	void __iomem *regs = mvi->regs_ex;  in mvs_64xx_spi_issuecmd()
724 static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)  in mvs_64xx_spi_waitdataready()  argument
726 	void __iomem *regs = mvi->regs_ex;  in mvs_64xx_spi_waitdataready()
739 static void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,  in mvs_64xx_fix_dma()  argument
744 	dma_addr_t buf_dma = mvi->bulk_buffer_dma;  in mvs_64xx_fix_dma()
754 static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time)  in mvs_64xx_tune_interrupt()  argument
756 	void __iomem *regs = mvi->regs;  in mvs_64xx_tune_interrupt()