Lines Matching refs:MVS_GBL_CTL
167 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
168 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
186 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
187 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
192 mw32_f(MVS_GBL_CTL, HBA_RST); in mvs_64xx_chip_reset()
200 if (!(mr32(MVS_GBL_CTL) & HBA_RST)) in mvs_64xx_chip_reset()
203 if (mr32(MVS_GBL_CTL) & HBA_RST) { in mvs_64xx_chip_reset()
441 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_enable()
442 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
450 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_disable()
451 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()