584 	dma_addr_t dma_coherent_handle;  in arcmsr_alloc_io_queue()  local
592 			&dma_coherent_handle, GFP_KERNEL);  in arcmsr_alloc_io_queue()
597 		acb->dma_coherent_handle2 = dma_coherent_handle;  in arcmsr_alloc_io_queue()
622 			&dma_coherent_handle, GFP_KERNEL);  in arcmsr_alloc_io_queue()
627 		acb->dma_coherent_handle2 = dma_coherent_handle;  in arcmsr_alloc_io_queue()
664 			&dma_coherent_handle, GFP_KERNEL);  in arcmsr_alloc_io_queue()
669 		acb->dma_coherent_handle2 = dma_coherent_handle;  in arcmsr_alloc_io_queue()
686 	dma_addr_t dma_coherent_handle;  in arcmsr_alloc_ccb_pool()  local
710 	dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);  in arcmsr_alloc_ccb_pool()
716 	acb->dma_coherent_handle = dma_coherent_handle;  in arcmsr_alloc_ccb_pool()
720 	acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;  in arcmsr_alloc_ccb_pool()
722 		cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);  in arcmsr_alloc_ccb_pool()
740 		dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;  in arcmsr_alloc_ccb_pool()
1885 	dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);  in arcmsr_free_ccb_pool()
3657 	dma_addr_t dma_coherent_handle;  in arcmsr_iop_confirm()  local
3668 		dma_coherent_handle = acb->dma_coherent_handle2;  in arcmsr_iop_confirm()
3671 		dma_coherent_handle = acb->dma_coherent_handle +  in arcmsr_iop_confirm()
3675 		dma_coherent_handle = acb->dma_coherent_handle;  in arcmsr_iop_confirm()
3678 	cdb_phyaddr = lower_32_bits(dma_coherent_handle);  in arcmsr_iop_confirm()
3679 	cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);  in arcmsr_iop_confirm()
3789 		dma_coherent_handle = acb->dma_coherent_handle2;  in arcmsr_iop_confirm()
3790 		cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff);  in arcmsr_iop_confirm()
3791 		cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16);  in arcmsr_iop_confirm()